ISL6142CB datasheet(4/23 Pages) INTERSIL

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Pin Descriptions

PWRGD (ISL6142; L Version) Pin 1 - This digital output is

an open-drain pull-down device and can be used to directly

enable an external module. During start-up the DRAIN and

GATE voltages are monitored with two separate comparators.

The first comparator looks at the DRAIN pin voltage compared

to the internal VPG reference (1.3V); this measures the

voltage drop across the external FET and sense resistor.

When the DRAIN to VEE voltage drop is less than 1.3V, the

first of two conditions required for the power to be considered

good are met. In addition, the GATE voltage monitored by the

second comparator must be within approximately 2.5V of its

normal operating voltage (13.6V). When both criteria are met

the PWRGD output will transition low and be latched in the

active state, enabling the external module. When this occurs

the two comparators discussed above no longer control the

output. However a third comparator continues to monitor the

DRAIN voltage, and will drive the PWRGD output inactive if

the DRAIN voltage raises more than 8V above VEE. In

addition, any of the signals that shut off the GATE (Over-

Voltage, Under-Voltage, Under-Voltage Lock-Out, Over-

Current time-out, pulling the DIS pin high, or powering down)

will reset the latch and drive the PWRGD output high to

disable the module. In this case, the output pull-down device

shuts off, and the pin becomes high impedance. Typically an

external pull-up of some kind is used to pull the pin high (many

brick regulators have a pull-up function built in).

PWRGD (ISL6152; H Version) Pin 1 - This digital output is

used to provide an active high signal to enable an external

module. The Power Good comparators are the same as

described above, but the active state of the output is

reversed (reference figure 37).

When power is considered good (both DRAIN and GATE are

normal) the output is latched in the active high state, the

DMOS device (Q3) turns on and sinks current to VEE through

a 6.2K

Ω resistor. The base of Q2 is clamped to V

EE to turn it

off. If the external pull-up current is high enough (>1mA, for

example), the voltage drop across the resistor will be large

enough to produce a logic high output and enable the external

module (in this example, 1mA x 6.2K

Ω = 6.2V).

Note that for all H versions, although this is a digital pin

functionally, the logic high level is determined by the external

pull-up device, and the power supply to which it is

connected; the IC will not clamp it below the VDD voltage.

Therefore, if the external device does not have its own

clamp, or if it would be damaged by a high voltage, an

external clamp might be necessary.

If the power good latch is reset (GATE turns off), the internal

DMOS device (Q3) is turned off, and Q2 (NPN) turns on to

clamp the output one diode drop above the DRAIN voltage to

produce a logic low, indicating power is no longer good.

FAULT Pin 2- This digital output is an open-drain, pull-down

device, referenced to VEE. It is pulled active low whenever

the Over-Current latch is set. It goes to a high impedance

state when the fault latch is reset by toggling the UV or DIS

pins. An external pull-up resistor to a logic supply (5V or

less) is required; the fault outputs of multiple IC’s can be

wire-OR’d together. If the pin is not used it should be left

open.

DIS Pin 3 - This digital input disables the FET when driven to

a logic high state. It has a weak internal pull-up device to an

internal 5V rail (10

µA), so an open pin will also act as a logic

high. The input has a nominal trip point of 1.6 V while rising,

and a hysteresis of 1.0V. The threshold voltage is referenced

to VEE, and is compatible with CMOS logic levels. A logic

low will allow the GATE to turn on (assuming the 4 other

conditions described in the GATE section are also true). The

DIS pin can also be used to reset the Over-Current latch

when toggled high to low. If not used the pin should be tied to

the negative supply rail (-VIN).

OV (Over-Voltage) Pin 4 - This analog input compares the

voltage on the pin to an internal voltage reference of 1.255 V

(nominal). When the input goes above the reference the

GATE pin is immediately pulled low to shut off the external

FET. The built in 25mV hysteresis will keep the GATE off until

the OV pin drops below 1.230V (the nominal high to low

threshold). A typical application will use an external resistor

divider from VDD to -VIN to set the OV trip level. A three-

resistor divider can be used to set both OV and UV trip

points to reduce component count.

UV (Under-Voltage) Pin 5 - This analog input compares the

voltage on the pin to an internal comparator with a built in

hysteresis of 135mv. When the UV input goes below the

nominal reference voltage of 1.120V, the GATE pin is

immediately pulled low to shut off the external FET. The

GATE will remain off until the UV pin rises above a 1.255V

low to high threshold. A typical application will use an

external resistor divider from VDD to -VIN to set the UV level

as desired. A three-resistor divider can be used to set both

OV and UV trip points to reduce component count.

The UV pin is also used to reset the Over-Current latch. The

pin must be cycled below 1.120V (nominal) and then above

1.255V (nominal) to clear the latch and initiate a normal

start-up sequence.

IS- Pin 6 - This analog pin is the negative input of the current

sense circuit. A sensing resistor (R7) is connected between

this pin and the VEE side of resistor R1. The ratio of R1/R7

defines the ISENSE to ISOUT current scaling factor. If current

sensing is not used in the application, the IS- pin should be

tied directly to the IS+ pin and the node should be left

floating.

ISL6142, ISL6152

ISL6142CB Datasheet(PDF) 4 Page - Intersil Corporation

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