ISL6142CB datasheet(16/23 Pages) INTERSIL

16 / 23 page

C1 and R3 prevent Q1 from turning on momentarily when

power is first applied. Without them, C2 would pull the gate

of Q1 up to a voltage roughly equal to VEE*C2/Cgs(Q1)

(where Cgs is the FET gate-source capacitance) before the

ISL6142/52 could power up and actively pull the gate low.

Place C1 in parallel with the gate capacitance of Q1; isolate

them from C2 by R3.

C1 =[(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the

FET’s minimum gate threshold, Vinmax is the maximum

operating input voltage, and Cgd is the FET gate-drain

capacitance.

R3 - its value is not critical, a typical value of 18k

Ω is

recommended but values down to 1K

Ω can be used. Lower

values of R3 will add delay to gate turn-on for hot insertion

and the single retry event following a hard fault.

R7/R8/R9 - are used to sense the load current (R7/R8) and

convert the scaled output current (ISOUT) to a voltage (R9)

that would typically be the input signal to an A to D converter.

R7 is connected between -IS and the R1 sense resistor.

These two resistors set the ISENSE (current through the

Rsense resistor) to ISOUT scaling factor based on equation 5

below. R8 does not effect the scaling factor but should match

R7 to minimize ISOUT error. Their tolerance should be +/-1%,

which will typically result in an output current error of less than

5% for a full scale condition. The trace layout is also critical to

obtain optimum performance. The traces connecting these

resistors to the device pins (IS+ and IS-) and to the R1 sense

resistor should be kept as short as possible, match in length,

and be isolated from the main current flow as illustrated in

figure 30.

R9 is used to convert the ISOUT current to voltage and is

connected between the ISOUT pin and -VIN. The current

flowing through the resistor (EQ. 5) should not exceed 600

µA

and the voltage on the CT pin will clamp at approximately 8V.

To select the appropriate resistor values for the application

the user must first define the R1 sense resistor value and the

maximum load current to be detected/measured. The value

of R7 should then be selected such that the maximum ISOUT

current is in the 400-500

µA range. For example, if the user

wanted to detect and measure fault currents up to the hard

fault comparator trip point (10A); the maximum ISOUT

current using the application components in figure 23 would

be [10A x (.02/400] = 500

µA. The value of R9 should be set

to accommodate the dynamic range of the A to D converter.

For this example, a 5K

Ω resistor would produce a full scale

input voltage to the converter of 2.5V (500

µA x 5KΩ).

Figures 32 and 33 illustrate the typical output voltage

response of the current sense circuit for the Over-Current

Time-out and hard fault single retry events.

R10 - is a pull-up resistor for the open drain FAULT output

pin which goes active low when the Over-Current latch is set

(Over-Current Time-Out). The output signal is referenced to

VEE and the resistor is connected to a positive voltage, 5V or

less, with respect to VEE. A typical value of 5KΩ is

recommended. A fault indicator LED can be placed in series

with the pull-up resistor if desired. The resistor value should

be selected such that it will allow enough current to drive the

LED adequately (brightness).

C3 - is the capacitor used to program the current limit time-

out period. When the Over-Current threshold is exceeded a

µA (nominal) current source will charge the C3 capacitor

from VEE to approximately 8.5V. When the voltage on the CT

pin exceeds the 8.5V threshold, the GATE pin will

immediately be pulled low with a 70ma pull down device, the

Over-Current latch will be set, and the FET will be turned off.

If the Over-Current condition goes away before the time-out

period expires, the CT pin will be pulled back down to VEE,

and normal operation will resume. Note that any parasitic

capacitance from the CT pin to -VIN will effectively add to

C3. This additional capacitance should be taken into account

when calculating the C3 value needed for the desired time-

out period.

The value of C3 can be calculated using equation 6 where dt

is the time-out period, dv is the CT pin threshold, and ICT is

the capacitor charging current.

Q2- is an N-channel logic FET used to drive the disable pin

(DIS). The DIS pin is used to enable/disable the external

pass transistor (Q1) by turning the GATE drive voltage on or

off. The DIS pin can also be used to reset the Over-Current

latch by toggling the pin high and then low. When Q2 is off,

the DIS pin is pulled high with an internal 500K

Ω resistor,

connected to an internal +5V (VEE + 5V) supply rail (10µA).

In this condition the GATE pin is low, and Q1 is turned off.

When Q2 is on, the DIS pin is pulled low to VEE allowing the

GATE pin to pull up and turn on Q1. The gate of Q2 will

typically be driven low (<1.5V) or High (>3.0V) with external

logic circuitry referenced to the negative input (-VIN).

Low-side Application

Although this IC was designed for -48V systems, it can also

be used as a low-side switch for positive 48V systems; the

operation and components are usually similar. One possible

difference is the kind of level shifting that may be needed to

interface logic signals to the IC. For example, many of the IC

functions are referenced to the IC substrate, connected to the

VEE pin, but this pin may be considered -48V or GND,

depending upon the polarity of the system. Also, the input or

output logic (running at 5V or 3.3V or even lower) might be

OUT

SENSE

-----------------------

(EQ. 5)

------

timeout

8.5V

----------------------

–

×10

(EQ. 6

ISL6142, ISL6152

ISL6142CB Datasheet(PDF) 16 Page - Intersil Corporation

ISL6142CB Datasheet(HTML) 16 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL