ISL6142CB datasheet(9/23 Pages) INTERSIL

9 / 23 page

Test Circuit and Timing Diagrams

FIGURE 2A. TYPICAL TEST CIRCUIT

FIGURE 2B. TEST CIRCUIT FOR TIMEOUT

FIGURE 3A. OV TO GATE TIMING

FIGURE 3B. UV TO GATE TIMING

FIGURE 3. OV AND UV TO GATE TIMING

FIGURE 4A. DRAIN TO PWRGD ACTIVE TIMING (ISL6142)

FIGURE 4B. DRAIN TO PWRGD ACTIVE TIMING (ISL6152)

FIGURE 4. DRAIN TO PWRGD/PWRGD TIMING

FIGURE 5A. GATE TO PWRGD ACTIVE (ISL6142)

FIGURE 5B. GATE TO PWRGD ACTIVE (ISL6152)

VEE

GATE

DRAIN

SENSE

PWRGD

VDD

VOV

VUV

48V

VDRAIN

VSENSE

ISL6142

FAULT

VDIS

4.99K

404

Ω

400

Ω

VEE

DRAIN

PWRGD

VDD

VOV

VUV

48V

VDRAIN

ISL6142

FAULT

GATE

SENSE

0.1K

0.90K

9.0K

GATE

tPHLOV

tPLHOV

1.255V

1.230V

13.6V

UV Pin

GATE

tPHLUV

tPLHUV

1.125V

1.255V

13.6V

tPHLDL

DRAIN

PWRGD

1.3V

1.0V

VPG

PWRGD

tPLHDL

1.3V

1.0V

DRAIN

VEE

VPG

tPHLGH

2.5V

1.0V

GATE

PWRGD

∆VGATE - VGATE = 0V

13.6V

VGH

tPLHGH

GATE

PWRGD

2.5V

1.0V

VPWRGD - VDRAIN = 0V

∆VGATE - VGATE = 0V

13.6V

VGH

ISL6142, ISL6152

ISL6142CB Datasheet(PDF) 9 Page - Intersil Corporation

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