ISL6590DR datasheet(6/24 Pages) INTERSIL

6 / 24 page

General Description

The ISL6590 is a multiphase digital controller optimized for

microprocessor core voltage generation in the 0.8375Vdc -

1.600Vdc output range and high current loading up to 150A

with a 12Vdc input. It is intended to be used as a chipset with

multiple ISL6580 power stages. The current per stage is up

to 25A and the switching frequency can operate from

250kHz to 1MHz. The adaptability of having a digital

controller with a serial data bus to the power stages means

that the control algorithms can be adjusted with software

instead of having to make hardware or board changes. All of

the features of the ISL6590 are available in applications that

require 3-6 phases of PWM (Pulse-Width Modulation) core

voltage regulation. For more information on the power stage,

consult the ISL6580 data sheet.

Block Diagram Overview

The ISL6590 contains functionality to control up to 6 power

stages with PWM core voltage regulation. The blocks

described follow the block diagram shown in Figure 1. For

additional help it would be useful to reference the block

diagram of the ISL6580, which is located in the ISL6580 data

sheet.

Asynchronous Serial Interface (ASI) (ATX, ARX)

This 2-wire serial data host interface is designed to transfer

command information from the designers PC to the

controller, such as adjustments to register settings. The ASI

is used during the design process to configure and test your

power supply settings. It allows the designer to change loop

coefficients to achieve the best response for their system

design. This serial bus runs at 115K baud rate to interface

with a host computer during testing.

Backside Serial Bus (BSB) (SDATA, SCLK)

The backside serial bus is a 2-wire communication between

the ISL6590 controller and the ISL6580 power ICs used for

transfer of control and status information. This bus is critical

for proper operation of the system, any miscommunications

will cause a bus error between the controller and power

stages and shutdown the power supply. A bus error can be

caused by poor routing of those lines or by a failed ISL6580.

Feedback (PWM, NDRIVE, ATR, IDIG, SOC, ERR)

The feedback control block implements the loop

compensation, hysteretic control, and switch driver. Defaults

for the loop compensation coefficients are retained in the

memory block. If the default values need to be optimized,

they can be adjusted using the ASI.

The PWM generator that drives NDRIVE and PWM derives

its waveform from a current balancing circuit that balances

the current to each phase. The current balancing circuit

requires information about the amount of current each phase

is supporting. This information is obtained using the 6-bit

current ADC in each ISL6580.

Each of the ISL6580s contains a 6-bit voltage ADC that can

be used to measure the difference between the core voltage

at the output and a reference voltage that is set by the VID

information. Even though each ISL6580 has the voltage

ADC, only one of them is required to use it.

When a large change in current occurs at the output load, a

large voltage transient also occurs. The ATRH and ATRL

levels are designed to trigger a temporary mode in which the

PWM generator aligns all phases or removes all phases in

order to quickly raise or lower the output voltage.

Controller Memory

The internal volatile memory provides control and status

registers which are reset to default states on each power up.

These registers can be altered with commands from the ASI,

the State Control and Fault Monitors, or the Serial Interface

with the ISL6580 Power ICs.

EEPROM Interface (MCS, MCLK, MDI, MDO)

An external EEPROM (non-volatile memory) can be used to

write custom information to the volatile memory. The non-

volatile memory can be modified via the ASI. The EEPROM

contains configuration values for a given design. The

ISL6590 uses the standard Serial Peripheral Interface

(SPI™) serial protocol for this memory. The EEPROM must

be at least a 2K byte memory. Larger memory can be used

without problems, however the ISL6590 will utilize only 2K

bytes.

Clock Distribution (OSC_IN, OSC_OUT)

The clock distribution block creates the internal system clock

from an external clock source such as a crystal oscillator. It

performs a 4x frequency multiplication of the external clock

frequency. The maximum clock input is 33.33MHz for an IC

sample rate of 133.3MHz. It generates the read/write clock

for the ASI. The system clock is provided to the ISL6580s via

the SYS_CLK pin.

State Control and Fault Monitoring (OUTEN,

VID[5:0], PWRGD)

Implements control of the power system state and processes

fault information from the ISL6580 Power IC. All fault

detection within the system is accomplished within each

individual ISL6580 and is communicated to the ISL6590 via

the Backside Serial Interface. ISL6590 detects the fault

through constant polling of the ISL6580 fault registers and

responds by tristating the outputs or shutting down the

system which then requires a power cycle and initiates a

softstart sequence.

Memory Bus Multiplexer

Controls the priority of data transfer to the volatile memory

(control registers) from both the ASI and the state control

and fault monitoring. The state control and fault monitoring is

given priority over the ASI.

ISL6590

ISL6590DR Datasheet(PDF) 6 Page - Intersil Corporation

ISL6590DR Datasheet(HTML) 6 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL