ISL6590DR datasheet(7/24 Pages) INTERSIL

7 / 24 page

Block Diagram Details

Feedback Control

At a minimum, there must be three ISL6580s available to

implement the following modes.

1. Regulation Mode (Voltage ADC)

2. Voltage Transient Mode (ATR Window Comparator)

3. Over/Under Voltage Mode (O/U Voltage Comparator)

Additional phases 4-6 are in normal conversion mode.

Located in the Feedback Control section of the ISL6590 is

an interface to the feedback information collected and

delivered by the analog ISL6580 power stages. To

understand the functionality of the ISL6590 feedback

algorithms, key blocks of the ISL6580 must be understood,

such as the ADC converters and the window comparator.

6-bit Current ADC (ISL6580)

A current ADC (Analog-to-Digital Converter) located in each

ISL6580 measures, converts, and transmits that driver’s

current back to the ISL6590 serially via the IDIG[6:1] bus.

The start of conversion is initiated on the falling edge of the

PWM input signal at the ISL6580 and the conversion takes

about 8 SYSCLK cycles. The SYSCLK signal is provided by

the ISL6590 to the ISL6580 and is equal to 4x the crystal

oscillator rate. The 6-bit current ADC is a successive

approximation converter, requiring one clock per bit, for a

total of 6 clocks. Another clock cycle is for transferring data

to the serial register. Since the PWM and SYSCLK may not

be phase related, one extra clock cycle may be required

depending on the alignment.

It is not possible to predict when the serial data will begin to

transfer on the IDIG bus, so a start bit is used to notify the

ISL6590 that data is coming. The start bit is followed by the

six data bits in descending order from the MSB. A bit is

transferred every two SYSCLK cycles. Since the PWM

signal is used as the start of conversion signal, a significant

glitch on the PWM signal during the conversion or data

transfer will initiate a new conversion and abort the present

conversion. The ISL6590 uses the serial current information

on the IDIG bus to calculate the average of all the phases,

compare it to the current of each phase, and balance the

phases by adjusting each PWM and NDRIVE signal as

necessary.

Because the start of conversion is dictated by the falling

edge of the PWM signal, the effective sample rate of the

current information is the PWM rate (typ<1MHz), even

though each bit is converted and transferred at SYSCLK/2 =

66.6MHz. All ISL6580s will return IDIG information,

regardless of their mode.

PWM

GENERATOR

CURRENT

AVERAGING

CURRENT

BALANCING

AVP

PID

CURRENT

FLASH

LOGIC

IDIG1

IDIG3

IDIG4

IDIG5

IDIG6

IDIG2

ATRH

ATRL

ISHARE

IERR

PIDOUT

ATRH

ATRL

IAVG

VERR

AVP0

6-BIT SERIAL

6-BIT OFFSET BINARY

NDRIVE[6:1]

PWM[6:1]

PARALLEL LINES

(FROM ERR SIGNAL - ISL6580 VOLTAGE ADC)

(FROM ISL6580 ATRH AND ATRL SIGNALS)

(TO ISL6580s)

FIGURE 2. FEEDBACK CONTROL DIAGRAM

ISL6590

ISL6590DR Datasheet(PDF) 7 Page - Intersil Corporation

ISL6590DR Datasheet(HTML) 7 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL