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UPD16633B Datasheet(PDF) 4 Page - NEC |
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UPD16633B Datasheet(HTML) 4 Page - NEC |
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4 / 20 page ![]() 4 µµµµPD16633B 4. PIN FUNCTIONS Pin Symbol Pin Name Description S1 to S312 Driver output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 Display data input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB R/L Shift direction control input These refer to the start pulse input/output pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R/L = H : STHR input, S1 →S312, STHL output R/L = L : STHL input, S312 →S1, STHR output STHR Right shift start pulse input/output R/L = H : Becomes the start pulse input pin. R/L = L : Becomes the start pulse output pin. STHL Left shift start pulse input/output R/L = H : Becomes the start pulse output pin. R/L = L : Becomes the start pulse input pin. CLK Shift clock input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 52nd clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. The initial-level driver’s 52nd clock becomes valid as the next-level driver’s start pulse is input. If 54th clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L ; The S2n–1 output uses V0 to V4 as the reference supply; The S2n output uses V5 to V9 as the reference supply. POL = H; The S2n–1 output uses V5 to V9 as the reference supply; The S2n output uses V0 to V4 as the reference supply. POL2 Data inversion POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted. V0 to V9 γ-corrected power supplies Input the γ-corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 TEST Test pin TEST = H or Open: Standard mode TEST = L: Test mode Please input “H” level. VDD1 Logic power supply 3.3 V ± 0.3 V VDD2 Driver power supply 10.0 V to 13.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding |
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