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UPD16633B Datasheet(PDF) 7 Page - NEC |
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UPD16633B Datasheet(HTML) 7 Page - NEC |
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7 / 20 page  7 µµµµPD16633B Figure 2-1. Relationship Between Input Data and Output Voltage: VDD2 > V0 > V1 > V2 > V3 > V4 > V5 Data DX5 DX4 DX3 DX2 DX1 DX0 Output Voltage 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0’ V1’ V2’ V3’ V4’ V5’ V6’ V7’ V0 V1 + (V0 – V1) × 4500/5300 V1 + (V0 – V1) × 3700/5300 V1 + (V0 – V1) × 2900/5300 V1 + (V0 – V1) × 2200/5300 V1 + (V0 – V1) × 1500/5300 V1 + (V0 – V1) × 900/5300 V1 + (V0 – V1) × 400/5300 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V8’ V9’ V10’ V11’ V12’ V13’ V14’ V15’ V1 V2 + (V1 – V2) × 3600/4000 V2 + (V1 – V2) × 3300/4000 V2 + (V1 – V2) × 3000/4000 V2 + (V1 – V2) × 2700/4000 V2 + (V1 – V2) × 2400/4000 V2 + (V1 – V2) × 2200/4000 V2 + (V1 – V2) × 2000/4000 10H 11H 12H 13H 14H 15H 16H 17H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V16’ V17’ V18’ V19’ V20’ V21’ V22’ V23’ V2 + (V1 – V2) × 1800/4000 V2 + (V1 – V2) × 1600/4000 V2 + (V1 – V2) × 1400/4000 V2 + (V1 – V2) × 1300/4000 V2 + (V1 – V2) × 1200/4000 V2 + (V1 – V2) × 1100/4000 V2 + (V1 – V2) × 1000/4000 V2 + (V1 – V2) × 900/4000 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V24’ V25’ V26’ V27’ V28’ V29’ V30’ V31’ V2 + (V1 – V2) × 800/4000 V2 + (V1 – V2) × 700/4000 V2 + (V1 – V2) × 600/4000 V2 + (V1 – V2) × 500/4000 V2 + (V1 – V2) × 400/4000 V2 + (V1 – V2) × 300/4000 V2 + (V1 – V2) × 200/4000 V2 + (V1 – V2) × 100/4000 20H 21H 22H 23H 24H 25H 26H 27H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V32’ V33’ V34’ V35’ V36’ V37’ V38’ V39’ V2 V3 + (V2 – V3) × 2600/2700 V3 + (V2 – V3) × 2500/2700 V3 + (V2 – V3) × 2400/2700 V3 + (V2 – V3) × 2300/2700 V3 + (V2 – V3) × 2200/2700 V3 + (V2 – V3) × 2100/2700 V3 + (V2 – V3) × 2000/2700 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V40’ V41’ V42’ V43’ V44’ V45’ V46’ V47’ V3 + (V2 – V3) × 1900/2700 V3 + (V2 – V3) × 1800/2700 V3 + (V2 – V3) × 1700/2700 V3 + (V2 – V3) × 1600/2700 V3 + (V2 – V3) × 1500/2700 V3 + (V2 – V3) × 1400/2700 V3 + (V2 – V3) × 1300/2700 V3 + (V2 – V3) × 1200/2700 30H 31H 32H 33H 34H 35H 36H 37H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V48’ V49’ V50’ V51’ V52’ V53’ V54’ V55’ V3 + (V2 – V3) × 1100/2700 V3 + (V2 – V3) × 1000/2700 V3 + (V2 – V3) × 900/2700 V3 + (V2 – V3) × 800/2700 V3 + (V2 – V3) × 700/2700 V3 + (V2 – V3) × 600/2700 V3 + (V2 – V3) × 400/2700 V3 + (V2 – V3) × 200/2700 V1’ V2’ V3’ V55’ V56’ V57’ V0 V3 r0 r1 r2 r3 r55 r56 r57 r54 V31’ r30 r31 V32’ V33’ r32 r33 V2 V58’ r59 V59’ r58 V60’ r60 V61’ r62 V62’ r61 V4’ V5’ V6’ r4 r5 r6 V7’ r7 V8’ V9’ r8 r9 V0’ V1 V5 r4-5 V63” 9 k Ω V4 V63’ 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V56’ V57’ V58’ V59’ V60’ V61’ V62’ V63’ V3 V4 + (V3 – V4) × 2300/2500 V4 + (V3 – V4) × 2100/2500 V4 + (V3 – V4) × 1800/2500 V4 + (V3 – V4) × 1500/2500 V4 + (V3 – V4) × 1200/2500 V4 + (V3 – V4) × 800/2500 V4 Caution Between V4 and V5 terminal is connected by using the resistor (9 k Ω Ω Ω Ω) in the chip. |
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