Z4 Core exception overview

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Machine check syndrome register (MCSR)

This register is the first register to check additional information about the cause of the

exception. There are three groups of machine check causes.

Machine check address register (MCAR)

MCAR register contains target address reporting the fault condition. It is updated only for

Asynchronous Machine check group when MCSR.MAV bit is cleared and it is valid only if

MCSR.MAV status flag is set. Otherwise the MCAR register cannot be used in the fault

analysis.

It is important to clear MCSR.MAV bit after reading MCAR register value to enable capture

of the address, in case of new asynchronous machine check fault.

Machine check MCSRR0 register

This register is updated by the HW in the beginning of the machine check interrupt. It stores

the address of the instruction that causes the error condition.

Table 2. Machine check register

Register

Content

MCSR (syndrome register)

Register indicates the source of machine check, this condition

gives the possibility to differentiate between them

MCAR (address capture)

Register contains some sort of machine check conditions, the

address for which the asynchronous type of the machine

check exception was raised.

Address valid only when MCSR.MAV bit was ‘0’ before the

exception, otherwise MCAR register is not updated.

MCSRR0 (Save/Restore register)

Address of the instruction that caused the exception. Once

the exception is finished (mcrfi instruction), program starts

execution with the same instruction, that was the cause of the

exception.

Table 3. Machine check causes

Machine check cause

Brief description

Error Report Machine check

(IF,LD,ST,G)

These exceptions are directly associated with the current

bit. It means that the exception is always taken whenever the

condition occurs. They differentiate among Instruction fetch, Data

store and load.

Non-maskable interrupt

(NMI)

enabled and NMI pin is driven low.

Asynchronous Machine check

(BUS_IREER, BUS_DRERR,

BUS_WRERR)

Exceptions reported by the subsystem, usually as bus error

and are cumulative. This machine check whether the exception

group triggers capture of the corresponding address to the MCAR

previously set, then the MCAR register is not affected.