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AN4417

Comparison of microcontroller behavior during ECC error

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Appendix A

Comparison of microcontroller behavior

during ECC error

Table 8 is a summary of the behavior of different 90nm microcontrollers in case of either

single or double bit error in the flash. To understand the table, the user should keep in mind

that flash is accessed in word line of 128-bit. Each time a master would like to access (read

/ code fetch) a location, which belongs to a certain word line, the whole word line is read out

of the flash. The word line consists of two double-words A and B. Each one double-word

contains its own ECC. Even there is always read complete word line, behavior of

microcontroller can differ regarding which double-word is addressed and which one contains

an ECC error.

One concrete word line starting at address 0x00030000 is chosen as an example.

The first 2 columns of the table represent the address location which can be accessed and

can be affected by single/double bit error. Each row represents a combination of access and

an ECC error:

•

The marked cells in the first 2 columns are affected by an ECC error.

•

Cells with the text ‘Accessed by master’ are actually accessed by one of the crossbar

master.

•

In addition, few cells are marked which highlights some differences in term of behavior.

The other columns contain reaction of selected registers, - separately for each

microcontroller.