AN1496 - APPLICATION NOTE

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2 - WRITING CODE FOR THE FLASH OF ST10 WITH 0.35

µm EMBEDDED FLASH

2.1 - ST10 Programming Constraints

Programming Language:

Direct addressing is not allowed for command sequences. All addresses of command cycles shall be

defined only with Register-indirect addressing mode.

As the compiler may generate indirect addressing, the part of the software that generates the commands

to the Flash should be written in assembly. Still part of the software that is not generating the

commands can be in higher level language (ex : C).

Indirect addressing :

For command instructions, address bit A14, A15, A16 and A17 are don’t care, provided the generated

address falls within the Flash memory space.

This allows to simplify the use of DPP registers when generating commands to the Flash : any DPP

already pointing to data in the Flash memory space can be used to write commands to the Flash.

– Tip : It is also possible to use the extended segment or extended page instructions for addressing the

Flash.

2.2 - Polling the Flash Erase Program Controller

As soon as the Erase Program Controller (EPC) receives the last command of a command sequence, it

starts execution of the command. During command execution, the EPC status is indicated by 2 sources :

– The Flash Status Register,

– The Read/Bust signal.

The Flash automatically resumes the read mode after the completion of the command.

2.2.1 - Ready/Busy Signal

The Ready/Busy (R/B) signal is connected to the XPER2 interrupt node (XP2IC). When R is high, the

Flash is busy with a Program or Erase operation and will not accept any additional program or erase

instruction. When R/B is Low, the Flash is ready for any Read/Write or Erase operation. The R/B will also

be Low when the memory is put in Erase Suspend mode.

This signal can be polled by reading XP2IC register, or can be used to trigger an interrupt when the Flash

goes from Busy to Ready.

This feature may not be available for all ST10 variants in 0.35

µm technology (ex : not available for

ST10F280). Please, check the product datasheet.

2.2.2 - Flash Status Register

The Flash Status register has been described in the previous chapter.

This method of polling ST10 embedded Flash is the one recommanded : the method will be implemented

on all ST10 variants in 0.35

µm technology.

2.3 - Flash Memory Mapping in ST10 Space

As defined for all ST10 derivatives, the lower 32 Kbyte part of the embedded Flash memory can be

mapped into 2 different segments.

The Flash mapping is controlled by bit ROMS1 in register SYSCON.

Note : the memory mapping of the other block is independant of bit ROMS1.

Table 2 : FLASH Memory Block Mapping

Block

Addresses (Segment 0)

Addresses (Segment 1)

Size (bytes)

0

1

2

00’0000h to 00’3FFFh

00’4000h to 00’5FFFh

00’6000h to 00’7FFFh

01’0000h to 01’3FFFh

01’4000h to 01’5FFFh

01’6000h to 01’7FFFh

16 K

8 K

8 K