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AN4070 Datasheet(PDF) 18 Page - STMicroelectronics |
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AN4070 Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 53 page ![]() DC-DC converter design AN4070 18/53 Doc ID 022934 Rev 1 The minimum value of capacitance required on the DC bus is calculated according to the following equation: Equation 34 where t1 is given by: Equation 35 A total capacitance of about twice the calculated value, rated at 450 V and having an operating temperature of 105 °C, is selected for the inverter implementation. The capacitor bank is realized with the parallel connection of four 22 µF, 450 V capacitors. The value of Lf is designed in order to limit the current ripple to about 20% of the nominal current value. The following equations have been used to calculate the filtering inductance value: Equation 36 where n is the number of inverter levels (+Vbus, 0 and -Vbus) and D is the inverter duty cycle. The filter capacitor value is selected to limit the exchange of reactive power below 5% of nominal active power: Equation 37 To avoid resonance problems for the filter, due to low and high order harmonics, the resonant frequency should be chosen in a range between ten times the line frequency and one half of the switching frequency. The resonant frequency of an LCL filter is given by: Equation 38 uF t V P C bus out bus 52 . 36 370 10 5 250 4 4 2 3 1 2 min = ⋅ ⋅ ⋅ = ⋅ ⋅ = − grid F ms t ⋅ = = 4 1 5 1 () mH f i D V V n L sw pk grid bus f 54 . 3 400 . 17 22 . 0 75 . 0 ) 325 380 ( 3 1 1 = ⋅ ⋅ − ⋅ = ⋅ Δ ⋅ − ⋅ = nF X C P V X P P f f C f active grid C active reactive 750 1 4232 5 . 12 230 05 . 0 05 . 0 2 2 = ⋅ ≤ Ω = = ⋅ ≥ ⋅ < ω f g f g f res C L L L L f ⋅ ⋅ + ⋅ ⋅ = π 2 1 |
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