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TN1200 Datasheet(PDF) 10 Page - STMicroelectronics |
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TN1200 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 16 page ![]() Soldering assembly recommendations TN1200 10/16 DocID027277 Rev 1 5 Soldering assembly recommendations 5.1 PCB design recommendations for multi-pads Flip Chips For optimum electrical performance and highly reliable solder joints, STMicroelectronics recommends the PCB design guidelines for each bumps configuration. Note: A too thick gold layer finishing on the PCB pad is not recommended (low joint reliability). To optimize the natural self centering effect of Flip Chip on PCB, PCB pad positioning and size have to be properly designed (see Figure 9). Figure 9. Footprint Micro vias An alternative to routing on the top surface is to route out on buried layers. To achieve this, the pads are connected to the lower layers using micro vias. Table 3. PCB design recommendations example. PCB pad design Non solder mask defined PCB pad size 80 µm / 100 µm maximum Solder mask clearance 25 µm minimum PCB pad finishing Cu - Ni (2-6 µm) - Au (0.2 µm max) or Cu OSP (Organic Substrate Protection) |
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