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AN1729 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN1729 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 10 page ![]() AN1729 APPLICATION NOTE 6/10 When the micro controller of the TV gives the standby command, the switch SW1 is open and the 14V output turns on the small signal bipolar transistor Q3. As a result, a big current (as compared to the current that flows during normal operation) is forced to flow in the LED of the opto-coupler and thereby in both the phototransistor and R9. As explained before, this big current will disable the gate driver of the L6565. When the gate driver is disabled the quiescent current is unchanged and, since no energy is coming from the self-supply circuit, the VCC capacitor (C4) will be discharged below the UVLO threshold after some time. Then the start-up generator will be enabled and a new start-up cycle will begin. The resulting behaviour will be a low frequency intermittent operation that we will refer to as "enhanced burst-mode operation". With such operation the regulation loop used in normal operation of the converter is skipped; another kind of regulation takes place. The Secondary output of the converter starts to rise until it reaches a threshold VOmax fixed by the Zener diode DZ3 as VDZ3 +VBE+Vd where VBE is the base emitter voltage of the small signal transistor Q3 (BC547) and Vd is the voltage drop of the diode D8 (1N4148) (we can neglect the voltage drop on resistor R21). At this point the gate driver of the controller is disabled and switching is stopped. The length of this idle period is fixed by the discharge time of the capacitor C4 as above explained. During this idle period the output voltages will go down and the minimum values that they reach depends on their individual load. In order to obtain some design equations we can divide the burst-mode period in three time intervals: – Phase 1. From the moment when the L6565 controller has been just turned off and the start-up circuit starts to re-charge the VCC capacitor C4, to the moment when the controller is turned on, that is the VCC voltage exceeds the turn-on threshold. – Phase 2. From when the L6565 is turned on until the transistor Q3 is turned on and the L6565 stops. – Phase 3.From when the L6565 stops to when the VCC voltage goes down under the low UVLO threshold and the L6565 is turned off. Our purpose is to obtain simple equations, so some approximations will be introduced. An optimisation can be done, looking at the measurement results, in order to have as good performance as possible. – Phase 1. After the VCC voltage has fallen below the UVLO off threshold, the start-up cycle begins. The high voltage low current Mos Q5 is on and the capacitor C4 is charged through it and the resistor RH3. The starting value of the voltage on C4 is the UVLO off threshold. The voltage value on C4 when the L6565 is turned on is the turn-on threshold. Their difference is the hysteresis VCCHys. Considering the equation 1 that gives the charging current of the capacitor C4 the charging time of C4 (Tch-C4) is the following: (Eq. 2) – Phase 2. When the L6565 is turned on the voltage on the secondary output is VOmin, the MOSFET starts switching and the output voltages rise. As soon Vout2 reaches the threshold VDZ3 + VBE + Vd the BJT Q3 will be turned on and the gate driver of the L6565 disabled. The duration of this switching phase is typically much shorter than the others and will be neglected. – Phase 3. The converter is stopped until the VCC voltage falls under the UVLO off threshold. Let's call Iq the quiescent current of the L6565; the time for discharging the C4 capacitor is: T ch C 4 – V th on – V th o ff – – () C4 ⋅ I st u p – -------------------------------------------------------------- Vcc Hys RH3 C 4 ⋅⋅ V Z V Dro p V th – + -------------------------------------------------- == |
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