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AN1895 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN1895 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 16 page ![]() Power stage design procedure AN1895 6/16 The diode RMS current is: The dissipation on the sense resistor will be 0.17·3.962=2.7W, which justifies the use of four resistors; the selected MOSFET is the STP12NM50, a 0.3 Ω/500V MDmesh™ type from STMicroelectronics, housed in a TO220 package; two of them will be paralleled to handle the rated power; the selected diode is an STTH806DTI, an 8A/600V Tandem diode, again from STMicroelectronics, housed in a TO220 package. All of them must be dissipated to keep their temperature within safe limits. As for the inductor, the core size will be determined by saturation since the ripple is relatively low. Assuming a peak flux density Bmax=0.3T, the minimum required Area- Product is: An E42 core (AP = 3.15 cm4) has been chosen. See table 3 for the complete inductor spec. The output capacitor is determined by the hold-up time requirement. Assuming a minimum voltage of 300V after the line drop, a minimum of 180 µF is needed and a 220µF/450V capacitor will be used. 9. The peak multiplier bias voltage VMULT @90V mains must meet the condition: , where 1.65 is the minimum slope of the multiplier characteristic associated to the error amplifier saturated high (see Figure 9 in [1]). With the selected value for Rsense (0.17 Ω): Choosing the ratio of the resistor divider that biases the multiplier input (pin 3, MULT) KP =8·10 -3 lets the peak voltage on the multiplier pin will go from 1V to 3V, thus meeting the above condition. The high-side resistor of the output divider that sets the output voltage is chosen on the basis of the maximum allowed overvoltage on the output. Considering 40V overvoltage, the high-side resistor must be 1M Ω (see [3] for details, in this respect the L6561 and the L6562 are exactly equal). The low-side resistor will then be 1M Ω · (400/2.5 - 1) =6.29k Ω; the 6.34kΩ standard value will be used. Based on the model given in [2], a compensation network made with an RC series (R = 6.8 k Ω, C = 1 µF) guarantees a minimum of 25° phase margin (with 9 Hz bandwidth) at minimum line and a bandwidth not exceeding 20 Hz (with 50° phase margin) at maximum line. I Qrms () Pin 0 k minVout ------------------------- 16k min 3 π ⋅ ------------------- 417 0.318 400 ⋅ ----------------------------- 16 0.318 ⋅ 3 π ⋅ -------------------------- 2.41A == = AP min 186 1k minKr – k minKr ---------------------------- Pin 0tOFF B max ------------------------- ⎝⎠ ⎜⎟ ⎛⎞ 1.31 ≈ 186 1 0.318 0.3 ⋅ – 0.318 0.3 ⋅ ------------------------------------- 417 3.18 10 6 – ⋅⋅ 0.3 ------------------------------------------- ⎝⎠ ⎛⎞ 1.31 2.92 [cm 4 ] == I LpkmaxRsense 1.65 ----------------------------------------- V MULTpk 3 V in RMS ()min V in RMS ()max ----------------------------------- ≤≤ 7.39 0.17 ⋅ 1.65 --------------------------- 0.761 V MULTpk 3 90 265 ---------- ⋅ ≤≤ 1.02 == |
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