AN2787 datasheet(16/37 Pages) STMICROELECTRONICS

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Configuration

AN2787

16/37

Figure 10.

JP3 phase control

The 120 deg phase shifting is the default configuration in which the inner clock is divided

and three pulses delayed by 120 deg are obtained to trigger the switching regulator loops.

The synchronous clocking allows all the regulators to start at the same pulse, avoiding the

jitter due to simultaneous turn-on and off of different sections, but increasing the overall

RMS input current.

7.3

JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin)

The JP4 jumper allows selecting the internal divider or the external divider for the 1.8 V

switching regulator. When the VFB_1S8 pin is connected directly to the output capacitor, the

internal divider is enabled and this section provides 1.8 V output voltage. When the

multifunction pin VFB_1S8 is tied to the central tap of an external divider, the switching

regulator becomes adjustable, with the following output voltage:

Equation 1

Figure 11.

JP4 1.8 V divider selection

120deg Phase Shifting

Synchronous

JP3

Vout

⋅

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

Internal Divider Enabled

External Divider Enabled

AN2787 Datasheet(PDF) 16 Page - STMicroelectronics