AN4671 datasheet(6/17 Pages) STMICROELECTRONICS

Part #	AN4671

Description	How to fine tune your SiC MOSFET gate driver to minimize losses

PDF	17 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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6 / 17 page

How to minimize switching losses

AN4671

6/17

DocID027654 Rev 1

Figure 3: Eoff vs. Rg at VDD=800 V, ID=20 A, VGS=-2 V to 20 V, Tj=25 °C

Obviously, as the gate resistance drops, the drain-source overshoot (peak voltage

exceeding the VDD) increases, but the SCT30N120 exhibits only slight overshoot variation

with gate resistance. The maximum VDS across the MOSFET increases by only 50 V when

the gate resistance moves in to the 1 to 10

Ω range, hence the voltage margin is at least

20%, even when Rg = 1

Ω. Parasitic inductance between the drain and the positive clamp

voltage should be minimized.

The following electrical waveform diagrams clearly depict the voltage overshoot and Eoff

variation with Rg.

Figure 4: Eoff at Rg=1

Ω, VDD=800 V, ID=20 A, VGS=-2 V to 20 V, Tj=25 °C

AN4671 Datasheet(PDF) 6 Page - STMicroelectronics