AN2100

Clock management

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If the MCLK clock divider is set to a prescaling value other than 1 (i.e. if RCLK frequency

differs from MCLK), it is not possible to access the RCCU registers since they are always

clocked by RCLK.

For non-intensive operations, PLL1 may be disabled; in addition CLK2 may be divided by a

factor of 16, to allow low-power operation while maintaining fast interrupt response.

(Bus clock) and cannot be disabled by software in order to guarantee basic functionality.

A 32 kHz oscillator is present to maintain a real-time-clock (RTC), with programmable

WAKEUP alarm. It may be deactivated if not required; when active it is not influenced by any

low-power-mode switch.

The HDLC peripheral can optionally receive its reference clock from an external pin, and

may dynamically change its frequency independently from CPU operation. An internal PLL

(PLL2) allows the use of a low-frequency external signal, thus reducing power consumption

and generated noise.

The USB Interface needs a precise 48 MHz clock reference. This may be generated either

externally through the USBCLK pin, or by the internal PLL2, multiplying an external

reference at lower speed, if PLL2 is not used by the HDLC interface.

If the USB interface is not used, set bits 0, 1 and 2 in the PCU_PLL2CR register to switch off

PLL2 (and reduce power consumption).

To reduce power consumption, bits 0, 1 and 3 in the RCCU_PER register must be reset by

the application software in the initialization phase. These bits are enabled by hardware at

reset for factory test purposes only.

2.1

Peripheral clock gating

It is possible to disable a peripheral clock by setting its corresponding bit in the APB Clock

Disable Register (APBn_CKDIS). Refer to the APB Bridge Registers section in the STR71x

reference manual.

The EMI and the USB Kernel clocks are stopped by resetting the corresponding bits in the

RCCU_PER register.

Caution:

After a device reset, to avoid extra power consumption, bits 0, 1 and 3 must be reset in the

RCCU_PER register in order to disable the reserved clocks used only for factory test

purposes.