Power supply

AN2100

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1.2

Internal regulators

Figure 2 provides a schematic view of the power management block of the STR71x.

Figure 2.

Power management block

1.

In normal operation, the switch connecting the V18 domain and the V18BKP domain is closed, it is opened

only during STANDBY mode (refer to Section 4)

1.2.1

Main voltage regulator (MVR)

The Main Voltage Regulator (MVR) is able to generate sufficient current for the device to

operate in any mode through ballast P-channel transistors located inside the I/O ring. It

includes a bandgap reference for thermal compensation and it has a static power

consumption of 100 µA (typical).

Note:

1

The MVR is automatically switched off in Standby mode.

2

The MVR can be configured (using the LPVRWFI bit in the PCU_PWRCR register) to

automatically switch off when the device enters Stop mode or LPWFI mode, leaving the Low

Power VR as the only power supply.

3

The MVR can be switched off using the VRBYP bit in the PCU_PWRCR register, In this

configuration the device is only powered by the Low Power VR, the maximum allowed

operation frequency is 1 MHz and the PLL is disabled.

4

When the VROK bit in the PCU_PWRCR register is set by hardware this indicates that the

main regulator output voltage is stabilized at the specification value.

A/D converter

Low Power Voltage Regulator

Main Voltage Regulator

StandbyMode I/Os

I/Os

Core

3.3 V

RTC and Standby Logic

Backup Block

32 kHz Oscillator

See note 1