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UPD6461GS Datasheet(PDF) 52 Page - NEC |
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UPD6461GS Datasheet(HTML) 52 Page - NEC |
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52 / 60 page ![]() 52 µPD6461, 6462 POWER-ON CLEAR SPECIFICATIONS VDD tPCLL 0 V VDD 0 V VDD 0.8 VDD 0.16 VDD PCL EXTERNAL CLOCK INPUT Timing for external clock input (valid when selected with mask option) Note 10% of the external clock cycle Example: When the external clock frequency is 8 MHz Clock cycle = 125 ns The maximum slew rate is 10% of 125 ns, giving 12.5 ns. Remarks 1. Keep the external clock in phase with the rising edges of Hsync. 2. Design the input of Hsync so that noise of more than 100 ns is suppressed. 3. When using an external clock, leave the OSCOUT pin open. Parameter PCL pin low level hold time Conditions Min. 10 Typ. Max. Unit µs Symbol tPCLL Parameter Time from external clock fall to synchro- nizing signal rise Time from synchronizing signal rise to external clock fall tS (rising slew rate) Conditions Min. 30 30 Typ. Max. Unit ns ns ns Symbol tC-H tH-C tS Note tC-H tH-C 50 % 50 % Hsync External clock 10 % tS 90 % |
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