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AN2586 Datasheet(PDF) 8 Page - STMicroelectronics |
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AN2586 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 28 page ![]() Power supplies AN2586 8/28 Doc ID 13675 Rev 7 Figure 2. Power supply scheme 1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1 µF) must be connected. 2. VREF+ is either connected to VDDA or to VREF. 3. N is the number of VDD and VSS inputs. 1.3 Reset and power supply supervisor 1.3.1 Power on reset (POR) / power down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from 2V. The device remains in the Reset mode as long as VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in the low- density, medium-density, high-density, XL-density, and connectivity line STM32F10xxx datasheets. Figure 3. Power on reset/power down reset waveform VBAT STM32F10xxx N × 100 nF VDD + 1 × 10 µF 100 nF + 1 µF 100 nF + 1 µF (note 1) Battery VBAT VREF+ VDDA VSSA VREF– VDD 1/2/3/.../N VSS 1/2/3/.../N VREF VDD ai14865b VDD POR PDR 40 mV hysteresis Temporization tRSTTEMPO RESET ai14364 |
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