STR91x vectored interrupt controller VIC

AN2593

6/15

1.

In the IRQ interrupt handler, the software should read the VIC0 vector address register

VIC0_VAR in order to determine the address of the interrupt service routine and jump

to it.

2.

If the interrupt originates from VIC0, then reading the VIC0 vector address register in

step 1 will update the priority logic of VIC0: so interrupts with the same or lower priority

levels will be masked by the VIC.

But if an interrupt originates from VIC1 then you must also perform a read from the

VIC1 vector address registerVIC1_VAR in order to update the priority logic in VIC1.

3.

After finishing the interrupt processing including the clearing of the interrupt flags, you

must write any value in the VIC0 vector address register if the interrupt originates from

VIC0, or in the VIC1 vector address register if the interrupt is from VIC1, this in order to

indicate to the VIC that interrupt processing has finished, so it can update the priority

logic: then a same or lower level interrupt will be able to interrupt the CPU.

Simple (non vectored) handling of IRQ interrupts

This method of handling IRQ interrupts does not use the VIC hardware priority

management, so this means you do not have to read or write the VIC0_VAR or VIC1_VAR

registers to update the hardware priority logic.

This method can be used when there is a need to give higher priority to a VIC1 interrupt

over a VIC0 interrupt.

The flow for simple (non vectored) IRQ handling is the following:

1.

An IRQ interrupt occurs.

2.

Branch to the interrupt handler.

3.

Read the VICs IRQ Status registers to determine the source that generated the

interrupt, and prioritize the interrupts if there are multiple active interrupt sources.

4.

Branch to the corresponding interrupt service routine.

5.

Execute the interrupt service routine.

6.

Clear the interrupt. If a software interrupt generated the request, you must write to the

VICx_SWINTCR register.

7.

Check the IRQ Status registers of both VICs to ensure that no other interrupt is active.

If there is an active request, go to Step 4.

8.

Return from the interrupt.