Daisy-chained vectored interrupt service routine limitation

AN2593

10/15

3

Daisy-chained vectored interrupt service routine

limitation

3.1

Description of the limitation

For daisy-chained interrupts, if the VAR of only one VIC is read, it does not update the

hardware priority in the other VIC. This means the daisy chained interrupt controller doesn't

realize the interrupt is being serviced and keeps the interrupt request active.

For daisy-chained interrupts, the processor must read the VAR register of both interrupt

controllers and branch to the addresses provided. However the address provided by reading

the daisy-chained VAR register must be manipulated to skip the interrupt preamble. If two

daisy chained interrupts occur soon after each other and the daisy chained VAR register

address isn't branched to, the interrupt controller priority logic may be updated incorrectly.

This may cause a low priority interrupt to be missed.

The ARM Prime cell support team has planned to add a new section 2.2.3 in the TRM

(ARM-DDI-0181E) titled 'Daisy-chained interrupt flow sequence' to provide information

about the handling of daisy-chained interrupts. Consequently ST is not planning to change

the interrupt handling scheme in the STR9 firmware library, instead, as recommended by

ARM, we propose a workaround for handling all daisy-chained interrupts properly (see

Section 3.4).

3.2

Impact on user applications

The above limitation can be considered a having a low severity level since problems may

occur only in a few specific timing conditions when handling nested interrupts on VIC1.

Hence, customers who do not use nested interrupts on VIC1, do not have to change their

software. They can safely continue with the interrupt handling as it is implemented in the

STR9 firmware library.

For those who are using nesting on VIC1 in their applications, they should apply the

sequence for servicing daisy-chained interrupts recommended by ARM and given here in

Section 3.3.

3.3

Daisy-chained interrupt flow sequence

As it was stated in a previous section, there are two daisy-chained VICs in the STR91x

device. VIC0 is directly connected to the CPU and VIC1 is connected to VIC0.

The daisy-chaining works as follows:

1.

An interrupt occurs.

2.

The ARM processor branches to either the IRQ or FIQ interrupt vector.

3.

If the interrupt is an IRQ, read the VICVectAddr Register in VIC0 and branch to the

interrupt service routine. You can do this using an LDR PC instruction. Reading the

VICVectorAddr register updates the interrupt controller’s hardware priority register.

4.

Stack the workspace

5.

If the interrupt is coming from a VIC1 source, read the VICVectAddr register in the

daisy chained interrupt controller VIC1. Reading the VICVectorAddr Register updates