Software recommendations for handling interrupts

AN2593

8/15

2.2

Handling IRQ interrupts

Note:

In this section, only vectored handling of interrupts is explained.

When an IRQ interrupt occurs CPU will jump to address 0x18.

Then user has two options for managing the IRQs, the first option is:

●

Jumping directly to the Interrupt service routine by doing a relative jump to the value

indicated in the VIC0 Vector Address register (mapped at 0xFFFFFF030):

@0x18

LDR PC, [PC, #-0xFF0]

If choosing this option, then you need to define your ISR as “irq” by adding the “__irq “

attribute when defining the interrupt service routine function, example:

__irq void TIM0_IRQHandler (void) //example with IAR EWARM

The attribute __irq which is compiler dependent is added in order to instruct the

preprocessor to add necessary code for saving the registers in the stack at the beginning of

the interrupt service routine and restoring the registers at the end of interrupt processing.

The second option for servicing interrupt is:

●

Jumping to an IRQHandler as a first step in which you perform a context save, then

jumping to the ISR after reading the VIC0 vector address register (VIC0_VAR).

@0x18

LDR PC, IRQHandler

...

IRQHandler:

; Save context

; Read ISR address from VIC0 vector Address Register

; Branch with Link to ISR

; Restore context

For both options, in the ISR code you will need to manage the VIC priority:

– If the interrupt comes from VIC0 then you will need to write any value to VIC0_VAR

register at the end of the interrupt processing in order to update the VIC priority.

There is no need to do a read of VIC0_VAR, this was done when jumping to the ISR.

– If the interrupt comes from VIC1 AND if nested interrupt management (and thus also

priority management) is needed then in this case you will need to do a read of

VIC1_VAR at the beginning of the ISR and a write to VIC1_VAR at the end of the ISR

processing in order to update the VIC1 priority logic.

2.3

Nested interrupt management

2.3.1

With interrupt nesting support

When supporting nested interrupts, an interrupt service routine can be interrupted by a

higher priority interrupt.

It is important to know that the ARM core will disable IRQs when an IRQ interrupt occurs. So

in order to be able to support interrupt nesting you must re-enable interrupts in the interrupt

service routine, then disable them when exiting the ISR.

Two inline assembly code macros should be used: IENABLE and IDISABLE.