CPLD design

AN2682 - Application note

6/15

The I2S signal combination chosen for this solution is:

●

Transmitter SD active on SCK falling edge

●

Receiver SD active on SCK falling edge

●

WS active on SCK falling edge

The CPLD brige functions in two modes:

1.

Configuration mode: When the Start signal is low, the interface waits for configuration

parameters. These parameters are transmitted through a three-bit register named

Conf_Reg:

Figure 5.

Conf_Reg content

The Transmit and Receive bits activate or disactivate the corresponding directions in or

out of the CPLD interface.

DW (Double Word), when set, enables the support of any data format from 17 to 32 bits

by setting a WS length of 32 bits instead of 16.

The configuration register is set by the MISO line clocked by the falling edge of the Conf

signal while Start is low.

2.

Communication mode: This mode is active when the Start signal is high. The

interface generates the SCLK and SCK signals with their associated delays. It also

controls the WS signal as well as the data lengths.

The CPLD implementation is illustrated in Figure 6.

Figure 6.

SPI to I2S CPLD bridge internal diagram

The solution is synthesized on ALTERA QUARTUSII software using a MAX3000A 32

macrocell device. The implementation is done with 17 macrocells.

The VHDL code implementation is provided with this AN for STR71x and STR750. The

STR750 VHDL code can also be used for the STR91x and STM32 microcontroller.

Receive

Transmit

bit 0

bit 1

bit 2

DW

Start

Conf

MISO

CLK

Conf_reg

Delay control

WS generator

I2S clock control

16 bits

32bits

WSt

Start

SCKi

WSi

SDi

SCK

WSo

SDo

MOSI

SCLK

Central

block

CLK

CLK

CLK

WSt

Start

TR enable 1

TR enable 2

CLK

Start

DW

Mode select

DW

MISO