STR711 implementation example

AN2682 - Application note

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3.2

STR711 firmware description

This section describes how to use the SPI to I2S bridge in your application firmware, the

description is based on the source code for STR71x provided with this application note.

First, the STR71x peripherals are initialized:

●

The TIM1 timer is configured in PWM mode with a period and duty cycle corresponding

to the user defined CLK frequency.

●

The BSPI0 is configured in slave mode, with falling edge clock (CPOL=0, CPHA=1), 16

bit format, 10-word Transmit and Receive FIFO depth, clock divider calculated to

correspond to the user-defined BSPI clock frequency and Transmit FIFO empty

interrupt enabled (or Receive FIFO full interrupt if receive-only mode is active).

●

The EIC interrupt controller is configured to enable BSPI interrupt IRQ with the highest

priority.

The STR71x microcontroller performs two main functions:

1.

Configuration function: the microcontroller gets the user-defined Conf_Reg register

value from the DEFINE statements, then sets the Start pin low and transmits the three

bits clocked by the Conf falling edge.

2.

Communication function: After setting the Start signal high, the microcontroller waits

for an internal interrupt indicating that the transmit FIFO is empty or that the receive

FIFO is full. Then in the interrupt handler, the transmit FIFO is loaded from the audio

file and the receive FIFO is read and loaded in the corresponding file. This whole

operation is done while the last word is being transmitted and received (bidirectional

BSPI shift register). This results in fluent data transfer with no delays or breaks.