Clock management

AN2857

10/31

Doc ID 15241 Rev 3

Figure 2.

Clock tree

The read-only CLK_CMSR register contains the current selection of master clock sources

(for core and peripherals). Selection of the ‘next’ master clock is made through the writable

CLK_SWR register, the content of which is copied into the CLK_CMSR register once the

change is effective (see details below). Refer to Table 2 for clock selection values.

HSE OSC

1 - 24 MHz

HSE ext

OSCOUT

CSS

OSCIN

EXTCLK

OPTION bit

HIS RC

16

MHz

LSI RC

128

kHz

HSIDIV[1:0]

/8

/

4

/

2

/

1

Master

clock

switch

/1

/2

/4

/8

/16

/32

/64

/128

CKM[7:0]

CPUDIV[2:0]

fCPU

fHSE

fHSI

fHSIDIV

fLSI

Peripheral clock

enable(11 bits)

To peripherals

To CPU and

window watchdog

To auto wakeup

and independent

watchdog

Prescaler

PRSC[1:0]

OPTION bits

CKAWUSEL

OPTION bit

/1, /2, ../8

CANDIV[2:0]

To beCAN

fHSI

fHSIDIV

fHSE

fLSI

fMASTER

fCPU

fCPU/2

fCPU/4

fCPU/8

fCPU/16

fCPU/32

fCPU/64

CCOSEL[3:0]

CCO

Configurable clock output

ai15045