DMA controller description

AN3117

6/28

Doc ID 16846 Rev 4

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DMA controller description

The STM8L05xxx/15xxx, STM8L162xx, STM8AL31xx/3Lxx DMA controller is a system

peripheral used for transferring data between the local memory and the main memory

without the intervention of the central processor unit (CPU).

Once the DMA registers have been configured, large blocks of data can be transferred at

high speed between peripherals and a memory, or from one memory location to another.

Moving data with the DMA keeps CPU resources free for other operations and allows

computation and data transfer concurrency.

This is especially useful in real-time computing applications where not stalling the CPU

during concurrent operations is critical, and when data processing and transfer must be

performed in parallel to achieve sufficient throughput.

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DMA main features

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Four DMA channels shared among several peripherals

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Three transfer directions

–

Peripheral to memory

–

Memory to peripheral

–

Memory to memory

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Hardware and software channel priorities which allow arbitration

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Programmable number of “data to be transferred” (up to 255 data blocks)

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Capability to increment and decrement memory addressing mode

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Optional interrupt on half transactions and end of transactions

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Two transfer block sizes (8-bit and 16-bit data) which are programmable by software.

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Circular buffer management (auto-reload mode)

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Capability to suspend and to resume DMA transfers

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Capability to operate in Low power modes (Wait for interrupt or Wait for event)

Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals

connected to the same DMA channel (see Table 3) cannot be used simultaneously when the

DMA controller is active.

The DMA controller performs direct memory transfers by sharing the address and data bus

with the STM8 core. The DMA request may stop CPU access to the bus for some bus

cycles, for example, when the CPU and DMA are targeting the same destination (memory or

peripheral).

The arbitration between DMA and CPU is performed inside the STM8 core. Refer to the

STM8 core description for further information.