AN3117 datasheet(8/28 Pages) STMICROELECTRONICS

Part #	AN3117

Description	This application note describes how to use the direct memory access

PDF	28 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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8 / 28 page

DMA controller description

AN3117

8/28

Doc ID 16846 Rev 4

Note:

ADC1 can be mapped on each of the four channels: depending on the

SYSCFG_RMPCR1[1:0] bits (please refer to the ADC chapter and the SYSCFG registers

chapter in the RM0031 reference manual). The default mapping is Channel 0.

TIM4 can be mapped on each of the four channels: depending on the

SYSCFG_RMPCR1[3:2] bits (please refer to the Timer chapter and the SYSCFG registers

chapter in the RM0031 reference manual). The default mapping is Channel 3.

Table 3.

Peripherals served by DMA and channel allocations (medium density

devices)

Peripheral

DMA Ch.0

request source

DMA Ch.1 request

source

DMA Ch.2 request

source

DMA Ch.3

request source

ADC1

EOC

SPI1

–

I2C1

–

USART1

–

DAC

–

TRIG

TIM1

CC3

CC4

TIM1_U/CC1/COM

CC2

TIM2

CC1

TIM2_U

CC2

TIM3

TIM3_U

CC1

CC2

TIM4

TIM4_U

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