Performance considerations

AN3117

10/28

Doc ID 16846 Rev 4

2

Performance considerations

The DMA controller performs direct memory transfers by sharing the address and data bus

with the STM8™ core. DMA requests may stop CPU accesses to the bus during some bus

cycles, when the CPU and the DMA are both targeting memory and peripheral. The

arbitration is performed inside the STM8 core.

In addition, the DMA controller can signal to the STM8 core that the current access must

have priority over the CPU. There are two ways to do this:

●

The application specifies the timeout duration (number of wait cycles starting from the

latest request) by configuring TO[5:0] bits in the DMA_GCSR register. The DMA then

waits until this timeout has elapsed before requesting from the core a high priority

access to the bus.

●

The application configures a channel so that it always takes priority over the CPU.

Refer to Section 4.6: DMA channel priority transfer example for more details.

2.1

DMA latency

Three operations are required to perform a DMA data transfer from peripheral to RAM (for

example SPI reception):

1.

DMA request arbitration and address computation

2.

Reading data from the peripheral (DMA source)

3.

Writing loaded data in RAM (DMA destination)

When transferring data from RAM to peripheral (for example SPI transmission), the

operations are performed in the opposite order:

1.

DMA request arbitration and address computation

2.

Reading data from RAM memory (DMA source)

3.

Writing data to the peripheral

t

S

t

A

t

ACC

t

RAM

++

=

where:

●

●

●

As a result, the total latency for 8-bit data transfer is 3 system clock cycles.