AN3342 datasheet(8/39 Pages) STMICROELECTRONICS

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Power supply

AN3342

8/39

Doc ID 18461 Rev 3

2.3

Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power-

down reset circuit. The monitoring voltage begins at 0.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltage (VDD)

reach its specified working area. This internal reset is maintained for a period of ~1ms in

order to wait for supply stabilization.

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a

reset release is defined in the electrical characteristics section of the product datasheets.

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the VPOR/PDR

threshold (isolated and repetitive events).

Recommendations

All VDD and VSS pins including VDDIO and VSSIO need to be properly connected to the power

supplies. These connections, including pads, tracks and vias should have the lowest

possible impedance. This is typically achieved with thick track widths and preferably

dedicated power supply planes in multi-layer printed circuit boards (PCBs).

In addition, the power supply pair should be decoupled with filtering ceramic capacitors (C)

at 100 nF with one chemical C (1..2 µF) in parallel on the STM8TL5xxx device. The ceramic

capacitors should be placed as close as possible to the appropriate pins, or below the

appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but

exact values depend on the application needs. Figure 2 shows the typical layout of such a

VDD/VSS pair.

Figure 2.

Typical layout of VDD/VSS pair

Via to VSS

Via to VDD

Cap

VDD VSS

STM8

AN3342 Datasheet(PDF) 8 Page - STMicroelectronics