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AN3342 Datasheet(PDF) 10 Page - STMicroelectronics

Part # AN3342
Description  Getting started with STM8TL5xxx
PDF  39 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN3342 Datasheet(HTML) 10 Page - STMicroelectronics

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Reset control
AN3342
10/39
Doc ID 18461 Rev 3
4
Reset control
4.1
Reset management overview
The reset pin is a 3.3 V bidirectional I/O (supplied by VDDIO). After startup it can be
programmed by software to be used as a general purpose output.
Its output buffer driving capability is fixed to IolMIN = 2 mA @ 0.45 V in the 1.65 V to 3.6 V
range which includes a ~40 k pull-up. Output buffer is reduced to the n-channel MOSFET
(NMOS). The receiver includes a glitch filter, whereas the output buffer includes a 20 µs
delay.
There are many reset sources, including:
●
External reset through the NRST pin
●
Power-on reset (POR): During power-on, the POR keeps the device under reset until
the supply voltage (VDD) reach the right voltage level.
●
Independent watchdog reset (IWDG)
●
Window watchdog reset (WWDG), featuring also software reset.
●
SWIM reset: An external device connected to the SWIM interface can request the
SWIM block to generate a microcontroller reset.
●
Illegal opcode reset: If a code to be executed does not correspond to any opcode or
prebyte value, a reset is generated.
Figure 3 shows a simplified functional I/O reset schematic.
Figure 3.
Reset management
4.1.1
Output characteristics
●
A valid pulse on the pin is guaranteed with a
 20 ns pulse duration on the internal
output buffer.
●
After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed
starting from the falling edge of A (output of the OR between the different reset
sources).
RPU
VDD_IO
Pulse
generator
(min 20 µs)
System reset
Filter
100 nF
External
reset circuit
NRST
MS18949V2
Illegal op code reset
SWIM reset
POR reset
IWDG/WWDG/software reset
Delay
STM8TL5xxx
(typ 40 k
Ω)



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