AN3427 datasheet(18/52 Pages) STMICROELECTRONICS

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Peripheral migration

AN3427

18/52

Doc ID 019001 Rev 1

In addition to the differences described in the table above, the following additional steps

need to be performed during the migration:

System clock configuration: when moving from F1 series to F2 series only a few

settings need to be updated in the system clock configuration code; mainly the Flash

settings (configure the right wait states for the system frequency, prefetch

enable/disable,...) or/and the PLL parameters configuration:

If the HSE or HSI is used directly as system clock source, in this case only the

Flash parameters should be modified.

If PLL (clocked by HSE or HSI) is used as system clock source, in this case the

Flash parameters and PLL configuration need to be updated.

MCO clock

source

– MCO pin (PA8)

– Connectivity Line: HSI, HSE,

PLL/2, SYSCLK, PLL2, PLL3

or XT1

– Other product lines: HSI,

HSE, PLL/2 or SYSCLK

– MCO1 pin (PA8): HSI,

HSE, LSE or PLL

– MCO2 pin (PC9): PLLI2S,

PLL, HSE or SYSCLK

– With configurable

prescaler, from 1 to 5, for

each output.

MCO configuration in F2 series

is different from F1:

– For MCO1, the prescaler is

configured through bits

RCC_CFGR[MCO1PRE] and

the selection of the clock to

output through bits

RCC_CFGR[MCO1]

– For MCO2, the prescaler is

configured through bits

RCC_CFGR[MCO2PRE] and

the selection of the clock to

output through bits

RCC_CFGR[MCO2]

Internal

oscillator

measurement

/ calibration

- LSI connected to TIM5 CH4

IC: can measure LSI w/ respect

to HSI/HSE clock

- LSI connected to TIM5 CH4

IC: can measure LSI w/

respect to HSI/HSE clock

- LSE connected to TIM5

CH4 IC: can measure HSI w/

respect to LSE clock

- HSE connected to TIM11

CH1 IC: can measure HSE

range w/ respect to HSI clock

There is no configuration to

perform in RCC registers.

Interrupt

- CSS (linked to NMI IRQ)

- LSIRDY, LSERDY, HSIRDY,

HSERDY, PLLRDY, PLL2RDY

and PLL3RDY (linked to RCC

global IRQ)

- CSS (linked to IRQ)

- LSIRDY, LSERDY, HSIRDY,

HSERDY, PLLRDY and

PLLI2SRDY (linked to RCC

global IRQ)

No change on SW configuration:

interrupt enable, disable and

pending bits clear are done in

RCC_CIR register.

Table 4.

RCC differences between STM32 F1 and STM32 F2 series

RCC main

features

STM32 F1 series

STM32 F2 series

Comments

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