Firmware description

AN3992

10/22

Doc ID 022369 Rev 3

3.3

Key derivation mode

AES is a symmetric cryptography algorithm. The AES hardware accelerator can compute a

derived key from an encryption key that is named “Decryption key”. The decryption key is

pre-computed to speed-up the decryption phase.

In this mode, the AES takes the encryption key as an input and provides the decryption key

as an output. This mode takes 320 clock cycles.

Figure 4.

AES hardware accelerator: key derivation mode

In the example above, the decryption key, computed from the “Ultralow Power” encryption

key, is “91 DF 30 53 7A E9 49 19 92 FF 8D F8 C4 9B B7 4D" (hex format).

The algorithm given in Figure 5 provides the steps needed to use the AES hardware.

MS19718V1

AES hardware accelerator:

key derivation mode

Encryption Key=

"ultra-low power.”

Decryption Key=

"91 DF 30 53 7A E9 49 19

92 FF 8D F8 C4 9B B7 4D”