RM0312 datasheet(181/275 Pages) STMICROELECTRONICS

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RM0312

Inter-integrated circuit (I2C) interface

200

Closing the communication

The master sends a NACK for the last byte received from the slave. After receiving this

NACK, the slave releases the control of the SCL and SDA lines. Then the master can send

a Stop/Re-Start condition.

•

In order to generate the non-acknowledge pulse after the last received data byte, the

ACK bit must be cleared just after reading the second last data byte (after second last

RXNE event).

•

In order to generate the Stop/Re-Start condition, software must set the STOP/ START

bit just after reading the second last data byte (after the second last RXNE event).

•

In case a single byte is to be received, the Acknowledge deactivation and the STOP

condition generation are made just after EV6 (in EV6-1 just after ADDR is cleared).

After the Stop condition generation, the interface goes automatically back to slave mode

(MSL bit cleared).

The procedures described below are recommended if the EV7-1 software sequence is not

completed before the ACK pulse of the current byte transfer.

These procedures must be followed to make sure that the:

•

ACK bit is set low on time, before the end of the last data reception

•

STOP bit is set high after the last data reception without reception of supplementary

data.

For 2-byte reception:

•

Wait until ADDR = 1 (SCL is stretched low until the ADDR flag is cleared).

•

Set ACK low and set POS high.

•

Clear the ADDR flag.

•

Wait until BTF = 1 (data in DR, data 2 in shift register, SCL stretched low until data 1 is

read).

•

Set STOP high.

•

Read data 1 and 2.

For N > 2-byte reception, from N-2 data reception:

•

Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until

data N-2 is read).

•

Set ACK low.

•

Read data N-2.

•

Wait until BTF = 1 (data N-1 in DR, data N in shift register, SCL stretched low until data

N-1 is read).

•

Set STOP high.

•

Read data N-1 and N.

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