Overview of 16-bit SDADC

AN4207

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Doc ID 023945 Rev 1

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Overview of 16-bit SDADC

2.1

Main features

STM32F37x/38x devices have three embedded Sigma-Delta Analog to Digital Converters

(SDADC). They can be synchronized together and each has the following main features:

●

Effective number of bits (ENOB) equal to 14 bits

●

5 differential input pairs, or 9 single-ended inputs, or a combination

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High-performance data throughput:

–

16.6 ksps input sampling rate when multiplexing between different channels

–

50 ksps input sampling rate for single-channel operation

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Programmable gain: x0.5, x1, x2, x4, x8, x16 and x32

●

2.1.1

Clock selection

The SDADC clock is supplied by SDADCCLK which divides the system clock (SYSCLK) by

a selectable prescaler: 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44 and 48.

The typical operating frequency of SDADC is 6 MHz in fast mode and 1.5 MHz in slow

mode.

Example:

If SYSCLK is set to 72 MHz, the SDADC divider should be set to SYSCLK/Typical

Frequency:

Fast speed mode: prescaler = 72 MHz / 6 MHz = 12

Low speed mode: prescaler = 72 MHz / 1.5 MHz = 48

2.1.2

Input modes

The SDADC has three possible input modes, that can be combined.

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Differential mode:

●

Single ended offset mode

●

Single ended zero reference mode

Differential mode

It is recommended to use differential mode when the sensors being used produce very

small signals that are very susceptible to noise. This is especially the case when using

thermocouple and bridge type sensors (pressure sensors).

In differential mode, the SDADC converts the difference between SDADCx_AINyP and

SDADCx_AINyM. The result can be either positive or negative depending on which input is

at higher voltage.

Note:

The SDADC can not measure negative voltages and the input voltage on each channel must

stay within the electrical limits of the device.

The input range is [-Vref/(2*gain), + Vref/(2*gain)] and the conversion value is in the range [-

32767, +32767]