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AN4651

Interconnection descriptions

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3.3

From ADC to TIM

ADCx (x=1 to 4) provides the trigger event through watchdog signals to advanced-control

timers (TIM1/TIM8/TIM20).

The output (from ADC) is on signals ADCx_AWDy_OUT (x = 1 to 4, y = 1 to 3 as there are

three analog watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external

trigger).

ADCx_AWDy_OUT is activated when the associated analog watchdog is enabled. This

internal hardware signal is set when a guarded conversion is outside the programmed

thresholds.

ADCx_AWDy_OUT signal is reset after the end of the next guarded conversion which is

inside the programmed thresholds or when disabling the ADC (when setting ADDIS=1).

TIMx_ETR is connected to ADCx_AWDy_OUT through bits in TIMx_OR registers. Figure 2

details the connections between TIMx and ADCx analog watchdogs.

1.

x means that there is a connection. Table cells with gray shading indicate that there is no connection.

TIM1

TIM8

TIM20

ADC1

x

ADC2

x

ADC3

xx

ADC4

x

x