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AN4651 Datasheet(PDF) 27 Page - STMicroelectronics |
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AN4651 Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 34 page  DocID027426 Rev 1 27/34 AN4651 Interconnection descriptions 33 3.16 From system errors to TIM Besides the comparators outputs, there are other sources that may be used as trigger for the internal break events of some timers (TIM1/TIM8/TIM20/TIM15/TIM16/TIM17). These sources are: the clock failure event generated by the clock security system (CSS), the PVD output (this feature is not available in STM32F3x8 devices), the SRAM parity error signal, the Cortex-M4 LOCKUP (Hardfault) output. The above-mentioned sources can be connected internally to TIMx_BRK_ACTH input, with x = 1,8,15,16,17,20. Table 13. Timers synchronization(1) Master/ Slave SLAVE TIM1 TIM8 TIM20 TIM2 TIM3 TIM4 TIM15 TIM5 TIM19 TIM12 TIM1 TIM8_ ITR0 TIM20_ ITR0 TIM2_ ITR0 TIM3_ ITR0 TIM4_ ITR0 TIM8 TIM20_ ITR1 TIM2_ ITR1 TIM4_ ITR3 TIM2 TIM1_ ITR1 TIM8_ ITR1 TIM3_ ITR1 TIM4_ ITR1 TIM15_ ITR0 TIM5_ ITR0 TIM19_ ITR0 TIM3 TIM1_ ITR2 TIM8_ ITR3 TIM2_ ITR2 TIM4_ ITR2 TIM15_ ITR1 TIM5_ ITR1 TIM19_ ITR1 TIM4 TIM1_ ITR3 TIM8_ ITR2 TIM20_ ITR2 TIM2_ ITR3(2) TIM3_ ITR3(2) TIM5_ ITR2 TIM12_ ITR0 TIM5 TIM3_ ITR2 TIM12_ ITR1 TIM13 TIM12_ ITR2 TIM14 TIM2_ ITR3 TIM3_ ITR3 TIM12_ ITR3 TIM15 TIM1_ ITR0 TIM20_ ITR3 TIM2_ ITR1 (3) TIM3_ ITR2(3) TIM4_ ITR3 (3) TIM5_ ITR3 TIM19_ ITR2 TIM16 TIM15_ ITR2 TIM19_ ITR3 TIM17 TIM1_ ITR3 TIM15_ ITR3 TIM19 TIM2_ ITR0 TIM3_ ITR0 TIM4_ ITR0 1. The gray shading in table cells means Not Applicable. 2. Not applicable for STM32F37x. 3. Only for STM32F37x. |
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