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ISPMACH4ACPLDFAMILY Datasheet(PDF) 47 Page - Lattice Semiconductor

Part # ISPMACH4ACPLDFAMILY
Description  High Performance E 2 CMOS In-System Programmable Logic
PDF  62 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPMACH4ACPLDFAMILY Datasheet(HTML) 47 Page - Lattice Semiconductor

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ispMACH 4A Family
47
100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64)
Top View
100-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
VCC
= Supply Voltage
TDI
= Test Data In
TCK
= Test Clock
TMS
= Test Mode Select
TDO
= Test Data Out
TRST = Test Reset
ENABLE = Program
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
TDI
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
TMS
TCK
GND
A1
A3
A5
A7
A9
A11
A13
A15
B15
B13
B11
B9
B7
B5
B3
B1
B7
B6
B5
B4
B3
B2
B1
B0
C0
C1
C2
C3
C4
C5
C6
C7
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
ENABLE
GND
D1
D3
D5
D7
D9
D11
D13
D15
C15
C13
C11
C9
C7
C5
C3
C1
G7
G6
G5
G4
G3
G2
G1
G0
F0
F1
F2
F3
F4
F5
F6
F7
M4A3-64/64
M4A3-128/64
M4A5-128/64
17466G-032a
I/O Cell
PAL Block
C7



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