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LT1432CS8 Datasheet(PDF) 12 Page - Linear Technology

Part # LT1432CS8
Description  5V High Efficiency Step-Down Switching Regulator Controller
PDF  28 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1432CS8 Datasheet(HTML) 12 Page - Linear Technology

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12
LT1432
Switching Waveforms in Burst Mode
In burst mode, the LT1432 amplifier is converted to a
comparator with hysteresis. This causes its VC pin current
drive to be either zero (output low), or full “on” at about
0.8mA (output high). The LT1271 therefore is either driven
to full on condition or forced into complete micropower
shutdown. This makes a dramatic reduction in quiescent
current losses because the switching regulator chip draws
supply current only during the relatively short “on” peri-
ods. This burst mode results in a battery drain of only
1.2mA with zero output load, even though the nominal
quiescent current of the switcher chip is 7mA. This low
battery drain is accomplished at the expense of higher
output ripple voltage, but the ripple is still well within the
normal requirements for logic chips.
Figure 11 shows burst mode output ripple at load currents
of 0 (top trace), and 50mA (bottom trace). Ripple ampli-
tude is nominally set by the 100mV hysteresis built into the
LT1432, but in most applications, other effects come into
play which can significantly modify this value. The first is
delay in turning off the switcher. This causes the output to
overshoot slightly and therefore increases output ripple.
Delay is caused by the compensation capacitors used to
maintain a stable loop in the normal mode. Another effect,
however, is the ESR of the output capacitor. The surge
current from the switcher creates a step across the capaci-
tor ESR which prematurely trips the LT1432 comparator,
reducing ripple amplitude. A second delay occurs in
turning the switcher back on when the output falls below
its lower level. This delay is somewhat longer, but because
the output normally falls at a much slower rate than it rises,
this delay is not significant until output current exceeds
10mA. Falling rate is set by the output capacitor (including
any secondary filter capacitor), and the actual load cur-
rent, dVOUT/dt = IOUT/COUT. The slope in the top traces
implies a load current of approximately 2mA. This is the
sum of the 1mA output quiescent current of the LT1432
and the 1mA drawn by the VC pin and shunted through the
internal Schottky diode during the switcher “off” period.
The bottom trace at IOUT = 50mA shows increased ripple
caused by turn-on delay. Note that ripple frequency has
increased from 50Hz to about 600Hz and amplitude has
S
APPLICATI
I FOR ATIO
100mV/DIV
100mV/DIV
5ms/DIV
Figure 11. Burst Mode Output Ripple Voltage
100mV/DIV
100mV/DIV
5ms/DIV
more than doubled. Figure 12 shows the same conditions
except that a 47k
Ω resistor is connected from the LT1271
VIN pin to the VC pin to provide more start-up current.
These additions reduce ripple amplitude at 50mA load
current to a value only slightly higher than the no-load
condition.
Although it is difficult to see in Figures 11 and 12, there is
a narrow spike on the leading edge of the ripple caused by
the burst current and capacitor ESR. Figure 13 shows this
spike in more detail, both with and without an output filter.
Figure 12. Burst Mode Output Ripple Voltage



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