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LT1611CS5 Datasheet(PDF) 4 Page - Linear Technology |
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LT1611CS5 Datasheet(HTML) 4 Page - Linear Technology |
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4 / 12 page ![]() 4 LT1611 PIN FUNCTIONS SW (Pin 1): Switch Pin. Minimize trace area at this pin to keep EMI down. GND (Pin 2): Ground. Tie directly to local ground plane. NFB (Pin 3): Negative Feedback Pin. Minimize trace area. Reference voltage is –1.23V. Connect resistive divider tap here. The suggested value for R2 is 10k. Set R1 and R2 according to: R V R OUT 1 123 123 2 45 10 6 = − + − . . .• SHDN (Pin 4): Shutdown Pin. Tie to 1V or more to enable device. Ground to shut the device down. VIN (Pin 5): Input Supply Pin. Must be locally bypassed. BLOCK DIAGRAM – + FF RQ S 0.15 Ω SW DRIVER COMPARATOR 2 SHUTDOWN SHDN 4 1 – + Σ RAMP GENERATOR RC CC 1.4MHz OSCILLATOR GND 1611 BD R6 40k R4 140k R3 30k Q2 x10 Q1 Q3 R5 40k VIN VIN 5 NFB CPL (OPTIONAL) R2 (EXTERNAL) R1 (EXTERNAL) VOUT NFB 3 A2 A = 3 A1 gm OPERATIO The LT1611 combines a current mode, fixed frequency PWM architecture with a –1.23V reference to directly regulate negative outputs. Operation can be best under- stood by referring to the block diagram of Figure 2. Q1 and Q2 form a bandgap reference core whose loop is closed around the output of the converter. The driven reference point is the lower end of resistor R4, which normally sits at a voltage of –1.23V. As the load current changes, the NFB pin voltage also changes slightly, driving the output of gm amplifier A1. Switch current is regulated directly on a cycle-to-cycle basis by A1’s output. The flip-flop is set at the beginning of each cycle, turning on the switch. When the summation of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscil- lations at duty factors greater than 50%) exceeds the VC signal, comparator A2 changes stage, resetting the flip- Figure 2 flop and turning off the switch. Output voltage decreases (the magnitude increases) as switch current is increased. The output, attenuated by external resistor divider R1 and R2, appears at the NFB pin, closing the overall loop. Frequency compensation is provided internally by RC and CC. Transient response can be optimized by the addition of a phase lead capacitor, CPL, in parallel with R1 in applica- tions where large value or low ESR output capacitors are used. As load current is decreased, the switch turns on for a shorter period each cycle. If the load current is further decreased, the converter will skip cycles to maintain output voltage regulation. The LT1611 can work in either of two topologies. The simpler topology appends a capacitive level shift to a |
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