10

LT1641

APPLICATIO S I FOR ATIO

TIMER

SENSE

GATE

87

6

54

2

1

3

D1

CMPZ

5248B

GND

PWRGD

FB

R5

10

Ω

5%

ON

R1

294k

1%

48V

UV = 37V

GND

1641 F14

R2

10.2k

1%

C2

0.68

µF

R6,

1k, 5%

0.01

Ω

C1

10nF

R3

143k

1%

R4

4.22k

1%

R7

47k

5%

+

220

µF

Q2

MMBT5551LT1

LT1641

ACTIVE LOW

ENABLE MODULE

ON/OFF

Q1

IRF530

Figure 14. Active Low Enable Module

Power Good Detection

The LT1641 includes a comparator for monitoring the

output voltage. The noninverting input (FB pin) is com-

pared against an internal 1.233V precision reference and

exhibits 80mV hysteresis. The comparator’s output

(PWRGD pin) is an open collector capable of operating

from a pull-up as high as 100V.

The PWRGD pin can be used to directly enable/disable a

power module with an active high enable input. Figure 14

shows how to use the PWRGD pin to control an active low

enable input power module. Signal inversion is accom-

plished by transistor Q2 and R7.

Supply Transient Protection

The LT1641 is 100% tested and guaranteed to be safe

from damage with supply voltages up to 100V. However,

spikes above 100V may damage the part. During a short-

circuit condition, the large change in currents flowing

through the power supply traces can cause inductive

voltage spikes which could exceed 100V. To minimize the

spikes, the power trace parasitic inductance should be

minimized by using wider traces or heavier trace plating

and a 0.1

GND. A surge suppressor at the input can also prevent

damage from voltage surges.