UPD7566ACSA datasheet(21/58 Pages) NEC

21 / 58 page

µPD7566A, 7566A(A)

2.11

TIMER/EVENT COUNTER

The timer/event counter mainly consists of an 8-bit count register.

Fig. 2-12 Timer/Event Counter

256

Note indicates that an instruction has been executed.

The 8-bit count register is a binary up-counter. The contents of this counter are incremented each time a count

pulse (CP) is input to the counter, and are cleared to 00H when TIMER instruction has been executed, when the

RESET signal has been input, or when overflow (i.e., counting from FFH to 00H) has occurred in the counter.

The following four count pulses can be selected by the clock mode register (see 2.10 Clock Control Circuit).

CP: CL x

, CL x

, P00

The count register always counts up as long as the count pulse is input to it. Therefore, the TIMER instruction

clears the contents of the count register to 00H and triggers a timer operation.

The count register contents are incremented in synchronization with CP (or the rising edge of the P00 signal,

when an external clock is selected). When the number of counts reaches 256, the count value is returned from FFH

to 00H. At this time, the count register generates an overflow signal (INTT), setting the INTT test flag (INTT RQF).

The count register then starts counting up from 00H.

Whether or not an overflow has occurred can be learned by testing the INT RQF flag, using the SKI instruction.

When the timer/event counter operates as a timer, the reference time for the timer is determined by the CP

frequency. The accuracy of the measured time is determined, when the system clock is selected, by the system

clock oscillation frequency. If the signal input through the P00 pin is selected as the clock, the accuracy is determined

by the frequency of the signal input to the P00 pin.

The contents of the count register can always be made ready by TCNTAM instruction. By using this instruction,

the current time for the timer can be checked, or it can be determined how many event pulses have been generated

so far by inputting the event pulses to the P00 pin and counting them (event counter operation).

The count pending circuit is to ignore changes in the count pulses (CPs) while TCNTAM instruction is executed.

This is necessary because, when TCNTAM instruction is used to read the contents of the count register, unstable

data may be read while the present count is being updated.

The timer/event counter operates using the system clocks (CL) or the signals input to the P00 pin as count pulses.

Therefore, the timer/event counter can be used to release the HALT mode, in which the supply of the CPU clock

ø is stopped (see 3. STANDBY FUNCTIONS).

Internal bus

8-BIT COUNT REG

Count

pending

circuit

TCNTAM

TIMER

RESET

CLR

INTT

(to test control circuit)

Note

UPD7566ACSA Datasheet(PDF) 21 Page - NEC

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