LTC2408C datasheet(13/36 Pages) LINER

13 / 36 page

LTC2404/LTC2408

Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may

be included in averaging or discarded without loss of

resolution.

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CSADC is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

In order to shift the conversion result out of the device,

CSADC must first be driven LOW. EOC is seen at the SDO

pin of the device once CSADC is pulled LOW. EOC changes

in real time from HIGH to LOW at the completion of a

conversion. This signal may be used as an interrupt for an

external microcontroller. Bit 31 (EOC) can be captured on

the first rising edge of SCK. Bit 30 is shifted out of the

device on the first falling edge of SCK. The final data bit

(Bit 0) is shifted out on the falling edge of the 31st SCK and

may be latched on the rising edge of the 32nd SCK pulse.

On the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating a new conversion cycle has been initiated. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the VIN pin is maintained within

the – 0.3V to (VCC + 0.3V) absolute maximum operating

range, a conversion result is generated for any input value

from – 0.125 • VREF to 1.125 • VREF. For input voltages

greater than 1.125 • VREF, the conversion result is clamped

to the value corresponding to 1.125 • VREF. For input

voltages below – 0.125 • VREF, the conversion result is

clamped to the value corresponding to – 0.125 • VREF.

APPLICATIONS INFORMATION

Figure 3. Typical Data Input/Output Timing

EOC

“0”

SDO

SCK/CLK

DIN

CSMUX/CSADC

MSB

LSB

EXT

SIG

BIT 30

BIT 31

BIT 0

24048 F03

HI-Z

DON’T CARE

tCONV

HI-Z

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CSADC pin is

LOW. This bit is HIGH during the conversion and goes

LOW when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW. The sign bit changes state during the zero code.

Bit 28 (forth output bit) is the extended input range (EXR)

indicator. If the input is within the normal input range

≤ VIN ≤ VREF, this bit is LOW. If the input is outside the

normal input range, VIN > VREF or VIN < 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2404/LTC2408 Status Bits

Bit 31

Bit 30

Bit 29

Bit 28

Input Range

EOC

DMY

SIG

EXR

VIN > VREF

011

0 < VIN ≤ VREF

010

VIN = 0

+/0–

1/0

VIN < 0

001

Bit 27 (fifth output bit) is the most significant bit (MSB).

Bits 27-4 are the 24-bit conversion result MSB first.

Bit 4 is the least significant bit (LSB).

LTC2408C Datasheet(PDF) 13 Page - Linear Technology

LTC2408C Datasheet(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL