The information in this document is subject to change without notice.

MOS INTEGRATED CIRCUIT

ATM LIGHT SAR CONTROLLER

1997, 1998

©

Document No. S12775EJ2V0DS00 (2nd edition)

Date Published May 1998 N CP(K)

Printed in Japan

DATA SHEET

The mark

shows major revised points.

DESCRIPTION

The

cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a

MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data,

this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The

µPD98409

conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.

FEATURES

•

Conforms to ATM Forum

•

PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz)

Conforms to PCI Local Bus Specification Revision 2.1

•

AAL-5 SAR sublayer and ATM layer functions

•

Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)

•

Supports up to 64 virtual channels (VC) (64-VC control memory)

•

Two traffic shapers for transmission scheduling

•

MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU

•

Receive FIFO of 12 cells

•

PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)

•

JTAG boundary scan test functions

•

0.35-

µm CMOS process, +5/+3.3-V power supply

- Bus interface +5 V : +5/+3.3-V power supply

- Bus interface +3.3 V : +3.3-V single power supply

ORDERING INFORMATION

Part Number

Package

µPD98409GN-LMU

240-pin plastic QFP (0.5-mm fine pitch) (32

× 32 mm)