+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

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13

• • •

• • •

• • •

• • •

PD0 CLOCKED IN

SSTRB

SCLK

CS

• • •

• • • •

•

Figure 8. External Clock Mode SSTRB Detailed Timing

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the analog-to-digital

conversion steps. SSTRB pulses high for one clock

period after the last bit of the control byte. Succes-

sive-approximation bit decisions are made and appear

at DOUT on each of the next 12 SCLK falling edges

(Figure 6). SSTRB and DOUT go into a high-impedance

state when CS goes high; after the next CS falling edge,

SSTRB outputs a logic low. Figure 8 shows the SSTRB

timing in external clock mode.

The conversion must complete in some minimum time,

or droop on the sample-and-hold capacitors may

degrade conversion results. Use internal clock mode if

the serial clock frequency is less than 100kHz, or if

serial clock interruptions could cause the conversion

interval to exceed 120µs.

Internal Clock

In internal clock mode, the MAX146/MAX147 generate

their own conversion clocks internally. This frees the µP

from the burden of running the SAR conversion clock

and allows the conversion results to be read back at the

• • •

• • •

• • •

• • •

CS

SCLK

DIN

DOUT

Figure 7. Detailed Serial-Interface Timing