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MAX196ACAI Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX196ACAI Datasheet(HTML) 10 Page - Maxim Integrated Products |
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10 / 16 page ![]() Input Format The control byte is latched into the device, on pins D7–D0, during a write cycle. Table 2 shows the control- byte format. Output Data Format The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When reading the output data, CS and RD must be low. How to Start a Conversion Conversions are initiated with a write operation, which selects the mux channel and configures the MAX196/ MAX198 for either a unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition inter- val or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external. The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3µs with fCLK = 2MHz) ends (see Figure 5). External Acquisition Use the external acquisition timing mode for precise con- trol of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, termi- nates acquisition and starts conversion on WR’s rising edge (Figure 6). However, if the second control byte contains ACQMOD = 1, an indefinite acquisition interval is restarted. The address bits for the input mux must have the same values on the first and second write pulses. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode section). How to Read a Conversion A standard interrupt signal, INT, is provided to allow the device to flag the µP when the conversion has ended and a valid result is available. INT goes low when con- version is complete and the output data is ready (Figures 5 and 6). It returns high on the first read cycle or if a new control byte is written. Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface 10 ______________________________________________________________________________________ tCS tCSWS tWR tACQI tCONV tDH tDS tINT1 tD0 tTR HIGH-Z HIGH-Z tCSRS tCSRH CS WR D7–D0 INT RD DOUT ACQMOD ="0" DATA VALID CONTROL BYTE tCSWH Figure 5. Conversion Timing Using Internal Acquisition Mode |
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