82P33724 SHORT FORM DATA SHEET

PORT SYNCHRONIZER FOR IEEE 1588 AND

SYNCHRONOUS ETHERNET

8

REVISION 1 09/23/14

2.1

RECOMMENDATIONS FOR UNUSED INPUT

AND OUTPUT PINS

2.1.1

INPUTS

Control Pins

All control pins have internal pull-ups or pull-downs; additional resis-

resistor can be used.

Single-Ended Clock Inputs

For protection, unused single-ended clock inputs should be tied to

ground.

Differential Clock Inputs

For applications not requiring the use of a differential input, both

*_POS and *_NEG can be left floating. Though not required, but for

2.1.2

OUTPUTS

Status Pins

For applications not requiring the use of a status pin, we recommend

bringing out to a test point for debugging purposes.

Single-Ended Clock Outputs

All unused single-ended clock outputs can be left floating, or can be

brought out to a test point for debugging purposes.

Differential Clock Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

18

TDO

O

tri-state

CMOS

TDO: JTAG Test Data Output

The test data are output on this pin. They are clocked out of the device on the falling edge of

TCK.

TDO pin outputs a high impedance signal except during the process of data scanning.

Power & Ground

2, 3, 4, 5, 10 11, 12

VDDA

Power

-

VDDA: Analog Core Power - +3.3V DC nominal

20, 24, 69, 72

VDDAO

Power

VDDAO: Analog Output Power - +3.3V DC nominal

27, 29, 64, 66

VDDDO

Power

VDDDO: Digital Output Power - +3.3V DC nominal

40, 62

VDDD

Power

VDDD: Digital Core Power - +3.3V DC nominal

42, 53

VDDD_1_8

Power

VDDD_1_8: Digital Core Power - +1.8V DC nominal

19,23

VSSAO

Ground

VSSAO: Ground

73 (e_PAD)

VSS

Ground

-

VSS: Ground

Other

58

IC

-

-

IC: Internal Connection

Internal Use. This pin must be left open for normal operation.

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description