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FT232H Datasheet(PDF) 28 Page - Future Technology Devices International Ltd. |
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FT232H Datasheet(HTML) 28 Page - Future Technology Devices International Ltd. |
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28 / 65 page ![]() Copyright © 2014 Future Technology Devices International Limited 28 Document No.: FT_000288 FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC Datasheet Version 1.81 Clearance No.: FTDI #199 Name Min Nom Max Units Comments t1 16.67 ns CLKOUT period t2 7.5 8.33 9.17 ns CLKOUT high period t3 7.5 8.33 9.17 ns CLKOUT low period t4 0 9 ns CLKOUT to RXF# t5 0 9 ns CLKOUT to read DATA valid t6 0 9 ns OE# to read DATA valid t7 7.5 16.67 ns OE# setup time t8 0 ns OE# hold time t9 7.5 16.67 ns RD# setup time to CLKOUT (RD# low after OE# low) t10 0 ns RD# hold time t11 0 9 ns CLKOUT TO TXE# t12 7.5 16.67 ns Write DATA setup time t13 0 ns Write DATA hold time t14 7.5 16.67 ns WR# setup time to CLKOUT (WR# low after TXE# low) t15 0 WR# hold time Table 4.1 FT245 Synchronous FIFO Interface Signal Timings This mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60 MHz CLKOUT clock for the external system to use. Note that Asynchronous FIFO mode must be selected in the EEPROM before selecting the Synchronous FIFO mode in software. 4.4.1 FT245 Synchronous FIFO Read Operation A read operation is started when the chip drives RXF# low. The external system can then drive OE# low to turn the data bus drivers around before acknowledging the data with the RD# signal going low. The first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored. 4.4.2 FT245 Synchronous FIFO Write Operation A write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst operation can be done on every clock providing TXE# is still low. The external system must monitor TXE# and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for data to be accepted. |
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