MAX5259EEE datasheet(5/20 Pages) MAXIM

5 / 20 page

+3V/+5V, Low-Power, 8-Bit Octal DAC

with Rail-to-Rail Output Buffers

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (MAX5259) (continued)

(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10k

Ω, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values

are at VDD = +3V, and TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Feedthrough

Code = 00 hex

0.1

nV-s

Digital-to-Analog Glitch Impulse

Code = 80 to code = 7F hex

nV-S

VREF = 2.5Vp-p at 1kHz centered at 1.5V

code = FF hex

Signal-to-Noise Plus Distortion

Ratio

SINAD

VREF = 2.5Vp-pat 10kHz centered at 1.5V

code = FF hex

Multiplying Bandwidth

VREF = 0.1Vp-p centered at VDD/2, -3dB

bandwidth

700

kHz

Wideband Amplifier Noise

µV

POWER REQUIREMENTS

Power-Supply Voltage

VDD

2.7

3.6

Supply Current

IDD

1.3

2.6

Shutdown Supply Current

ISHDN

0.24

µA

TIMING CHARACTERISTICS (MAX5258)

(VREF = +4.096V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and

TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

VDD Rise-to-CS Fall-Setup Time

tVDCS

µs

LDAC Pulse Width Low

tLDAC

CS Rise-to-LDAC Fall-Setup Time

(Note 4)

tCLL

CS Pulse Width High

tCSW

SCLK Clock Frequency (Note 5)

fCLK

MHz

SCLK Pulse Width High

tCH

SCLK Pulse Width Low

tCL

CS Fall-to-SCLK Rise-Setup Time

tCSS

SCLK Rise-to-CS Rise-Hold Time

tCSH

0ns

DIN to SCLK Rise-to-Setup Time

tDS

DIN to SCLK Rise-to-Hold Time

tDH

0ns

SCLK Rise-to-DOUT Valid

Propagation Delay (Note 6)

tDO1

200

SCLK Fall-to-DOUT Valid

Propagation Delay (Note 7)

tDO2

210

CS Rise-to-SCLK Rise-Setup

Time

tCS1

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