General Description

The MAX5270 contains eight 13-bit, voltage-output digi-

tal-to-analog converters (DACs). On-chip precision out-

put amplifiers provide the voltage outputs. The device

operates from +12V/-12V supplies. Its output voltage

swing ranges from 0V to +8.192V and is achieved with

no external components. The MAX5270 has three pairs

of differential reference inputs; two of these pairs are

connected to two DACs each, and a third pair is con-

nected to four DACs. The references are independently

controlled, providing different full-scale output voltages

to the respective DACs. The MAX5270 operates within

The MAX5270 features double-buffered interface logic

with a 13-bit parallel data bus. Each DAC has an input

latch and a DAC latch. Data in the DAC latch sets the

output voltage. The eight input latches are addressed

with three address lines. Data is loaded to the input

latch with a single-write instruction. An asynchronous

load input (LD) transfers data from the input latch to the

DAC latch. The LD input controls all DACs; therefore, all

DACs can be updated simultaneously by asserting the

LD pin.

An asynchronous CLR input sets the output of all eight

DACs to the respective DUTGND input of the op amp.

Note that CLR is a CMOS input, which is powered by

The “A” grade of the MAX5270 has a maximum INL of

±2LSBs, while the “B” grade has a maximum INL of

±4LSBs. Both grades are available in 44-pin MQFP

packages.

Applications

Industrial Process Controls

Arbitrary Function Generators

Avionics Equipment

Minimum Component Count Analog Systems

Digital Offset/Gain Adjustment

SONET Applications

Automatic Test Equipment (ATE)

Features

o Full 13-Bit Performance Without Adjustments

o Eight DACs in a Single Package

o Buffered Voltage Outputs

o Voltage Swing Between 0 and +8.192V

o 22µs Output Settling Time

o Drives up to 10,000pF Capacitive Load

o 30mV Low Output Glitch

o Low Power Consumption: 10mA (typ)

o Small 44-Pin MQFP Package

o Double-Buffered Digital Inputs

o Asynchronous Load Updates All DACs

Simultaneously

o Asynchronous CLR Forces All DACs to DUTGND

Potential

Octal, 13-Bit Voltage-Output DAC

with Parallel Interface

DUTGNDGH

OUTH

REFGH-

REFGH+

CLR

D12

D11

D10

D9

D8

DUTGNDAB

OUTA

REFAB-

REFAB+

LD

A2

A1

A0

CS

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

MQFP-44

MAX5270

TOP VIEW

PART

MAX5270ACMH

MAX5270BCMH

0°C to +70°C

0°C to +70°C

TEMP. RANGE

PIN-

PACKAGE

44 MQFP

44 MQFP

Functional Diagram appears at end of data sheet.

Pin Configuration

Ordering Information

INL

(LSB)

±2

±4

MAX5270AEMH

-40°C to +85°C

44 MQFP

±2

MAX5270BEMH

-40°C to +85°C

44 MQFP

±4

19-1711; Rev 1; 1/01

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.